Cited By
View all- Tao ZShi YHuo YYe RLi ZHuang LWu CBai NYu ZLin THe L(2024)AMSNet: Netlist Dataset for AMS Circuits2024 IEEE LLM Aided Design Workshop (LAD)10.1109/LAD62341.2024.10691781(1-5)Online publication date: 28-Jun-2024
KATO: Knowledge Alignment And Transfer for Transistor Sizing Of Different Design and Technology
Article No.: 161, Pages 1 - 6
Abstract
Automatic transistor sizing in circuit design continues to be a formidable challenge. Despite that Bayesian optimization (BO) has achieved significant success, it is circuit-specific, limiting the accumulation and transfer of design knowledge for broader applications. This paper proposes (1) efficient automatic kernel construction, (2) the first transfer learning across different circuits and technology nodes for BO, and (3) a selective transfer learning scheme to ensure only useful knowledge is utilized. These three novel components are integrated into BO with Multi-objective Acquisition Ensemble (MACE) to form Knowledge Alignment and Transfer Optimization (KATO) to deliver state-of-the-art performance: up to 2x simulation reduction and 1.2x design improvement over the baselines.
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Index Terms
- KATO: Knowledge Alignment And Transfer for Transistor Sizing Of Different Design and Technology
Index terms have been assigned to the content through auto-classification.
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Published: 07 November 2024
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View all- Tao ZShi YHuo YYe RLi ZHuang LWu CBai NYu ZLin THe L(2024)AMSNet: Netlist Dataset for AMS Circuits2024 IEEE LLM Aided Design Workshop (LAD)10.1109/LAD62341.2024.10691781(1-5)Online publication date: 28-Jun-2024
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