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Mixed-Size 3D Analytical Placement with Heterogeneous Technology Nodes

Published: 07 November 2024 Publication History

Abstract

This paper proposes a mixed-size 3D analytical placement framework for face-to-face stacked integrated circuits fabricated with heterogeneous technology nodes and connected by hybrid bonding technology. The proposed framework efficiently partitions a given netlist into two dies and optimizes the positions of each macro, standard cell, and hybrid bonding terminal (HBT). A multi-technology objective function and a multi-technology density penalty calculation process are adopted to handle the heterogeneous-technology-node constraints during mixed-size 3D global placement. Furthermore, a 3D objective function is used to refine the placement result during HBT-cell co-optimization. Our placer achieves the best results for all contest test cases compared with the participating teams at the 2023 CAD Contest at ICCAD on 3D Placement with Macros.

References

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Z.-W. Jiang, T.-C. Cheny, T.-C. Hsuy, H.-C. Chenz, and Y.-W. Chang, "NTUplace2: A hybrid placer using partitioning and analytical techniques," in Proceedings of International Symposium on Physical Design, San Jose, California, April 2006.

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      cover image ACM Conferences
      DAC '24: Proceedings of the 61st ACM/IEEE Design Automation Conference
      June 2024
      2159 pages
      ISBN:9798400706011
      DOI:10.1145/3649329
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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      Published: 07 November 2024

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      Author Tags

      1. face-to-face stacked integrated circuits
      2. heterogeneous integration
      3. analytical placement

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      June 23 - 27, 2024
      CA, San Francisco, USA

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