More Web Proxy on the site http://driver.im/

research-article

eHDL: Turning eBPF/XDP Programs into Hardware Designs for the NIC

Authors:

Alessandro Rivitti,

Roberto Bifulco,

Angelo Tulumello,

Salvatore PontarelliAuthors Info & Claims

ASPLOS 2023: Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3

Pages 208 - 223

https://doi.org/10.1145/3582016.3582035

Published: 25 March 2023 Publication History

Abstract

Scaling network packet processing performance to meet the increasing speed of network ports requires software programs to carefully leverage the network devices’ hardware features. This is a complex task for network programmers, who need to learn and deal with the heterogeneity of device architectures, and re-think their software to leverage them. In this paper we make first steps to reverse this design process, enabling the automatic generation of tailored hardware designs starting from a network packet processing program. We introduce eHDL, a high-level synthesis tool that automatically generates hardware pipelines from unmodified Linux’s eBPF/XDP programs. eHDL is designed to enable software developers to directly define and implement the hardware functions they need in the NIC. We prototype eHDL targeting a Xilinx Alveo U50 FPGA NIC, and evaluate it with a set of 5 eBPF/XDP programs. Our results show that the generated pipelines are efficient in terms of required hardware resources, using only 6.5%-13.3% of the FPGA, and always achieve the line rate forwarding throughput with about 1 microsecond of per-packet forwarding latency. Compared to other network-specific high-level synthesis tool, eHDL enables software programmers with no hardware expertise to describe stateful functions that operate on the entire packet data. Compared to alternative processor-based solutions that perform eBFP/XDP offloading to a NIC, eHDL provides 10-100x higher throughput.

References

[1]

2019. The CAIDA Anonymized Internet Traces Dataset. https://www.caida.org/catalog/datasets/passive_dataset/

[2]

Chris Arges. 2023. How We Used eBPF to Build Programmable Packet Filtering in Magic Firewall. https://blog.cloudflare.com/programmable-packet-filtering-with-magic-firewall/

[3]

Pat Bosshart, Dan Daly, Glen Gibb, Martin Izzard, Nick McKeown, Jennifer Rexford, Cole Schlesinger, Dan Talayco, Amin Vahdat, George Varghese, and David Walker. 2014. P4: Programming Protocol-Independent Packet Processors. SIGCOMM Comput. Commun. Rev., 44, 3 (2014), July, 87–95. issn:0146-4833 https://doi.org/10.1145/2656877.2656890

Digital Library

[4]

Pat Bosshart, Glen Gibb, Hun-Seok Kim, George Varghese, Nick McKeown, Martin Izzard, Fernando Mujica, and Mark Horowitz. 2013. Forwarding metamorphosis: Fast programmable match-action processing in hardware for SDN. ACM SIGCOMM Computer Communication Review, 43, 4 (2013), 99–110.

Digital Library

[5]

Marco Spaziani Brunella, Giacomo Belocchi, Marco Bonola, Salvatore Pontarelli, Giuseppe Siracusano, Giuseppe Bianchi, Aniello Cammarano, Alessandro Palumbo, Luca Petrucci, and Roberto Bifulco. 2020. hXDP: Efficient Software Packet Processing on FPGA NICs. In 14th USENIX Symposium on Operating Systems Design and Implementation (OSDI 20). 973–990.

[6]

Derek Chiou. 2017. The microsoft catapult project. In 2017 IEEE International Symposium on Workload Characterization (IISWC). 124–124.

[7]

Sean Choi, Muhammad Shahbaz, Balaji Prabhakar, and Mendel Rosenblum. 2020. λ -nic: Interactive serverless compute on programmable smartnics. In 2020 IEEE 40th International Conference on Distributed Computing Systems (ICDCS). 67–77.

[8]

Cilium. 2023. Cilium - Linux Native, API-Aware Networking and Security for Containers. https://cilium.io/

[9]

Philippe Coussy, Daniel D Gajski, Michael Meredith, and Andres Takach. 2009. An introduction to high-level synthesis. IEEE Design & Test of Computers, 26, 4 (2009), 8–17.

Digital Library

[10]

DPDK. 2023. Data Plane Development Kit. https://www.dpdk.org//

[11]

Facebook. 2018. Katran source code repository. https://github.com/facebookincubator/katran

[12]

Jiawei Fei, Chen-Yu Ho, Atal N. Sahu, Marco Canini, and Amedeo Sapio. 2021. Efficient Sparse Collective Communication and Its Application to Accelerate Distributed Deep Learning. In Proceedings of the 2021 ACM SIGCOMM 2021 Conference (SIGCOMM ’21). Association for Computing Machinery, New York, NY, USA. 676–691. isbn:9781450383837 https://doi.org/10.1145/3452296.3472904

Digital Library

[13]

Daniel Firestone, Andrew Putnam, Sambhrama Mundkur, Derek Chiou, Alireza Dabagh, Mike Andrewartha, Hari Angepat, Vivek Bhanu, Adrian Caulfield, and Eric Chung. 2018. Azure accelerated networking: Smartnics in the public cloud. In 15th USENIX Symposium on Networked Systems Design and Implementation (NSDI 18). 51–66.

Digital Library

[14]

Romain Fontugne, Pierre Borgnat, Patrice Abry, and Kensuke Fukuda. 2010. MAWILab: Combining Diverse Anomaly Detectors for Automated Anomaly Labeling and Performance Benchmarking. In ACM CoNEXT ’10. Philadelphia, PA. 12 pages.

[15]

Alex Forencich, Alex C Snoeren, George Porter, and George Papen. 2020. Corundum: an open-source 100-Gbps NIC. In 2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). 38–46.

[16]

Fungible. 2021. Fungible F1 Data Processing Unit. https://www.fungible.com/wp-content/uploads/2021/09/PB0028.02.12020914-Fungible-F1-Data-Processing-Unit.pdf

[17]

Xiangyu Gao, Taegyun Kim, Aatish Kishan Varma, Anirudh Sivaraman, and Srinivas Narayana. 2019. Autogenerating fast packet-processing code using program synthesis. In Proceedings of the 18th ACM Workshop on Hot Topics in Networks. 150–160.

Digital Library

[18]

Hubble github repository. 2023. https://github.com/cilium/hubble

[19]

Toke Høiland-Jørgensen, Jesper Dangaard Brouer, Daniel Borkmann, John Fastabend, Tom Herbert, David Ahern, and David Miller. 2018. The EXpress Data Path: Fast Programmable Packet Processing in the Operating System Kernel. In Proceedings of the 14th International Conference on Emerging Networking EXperiments and Technologies (CoNEXT ’18). Association for Computing Machinery, New York, NY, USA. 54–66. isbn:9781450360807 https://doi.org/10.1145/3281411.3281443

Digital Library

[20]

Stephen Ibanez, Gordon Brebner, Nick McKeown, and Noa Zilberman. 2019. The p4-> netfpga workflow for line-rate packet processing. In Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. 1–9.

Digital Library

[21]

Intel. 2023. Intel Infrastructure Processing Unit (Intel IPU) and SmartNICs. https://www.intel.com/content/www/us/en/products/network-io/smartnic.html

[22]

Jakub Kicinski and Nicolaas Viljoen. 2016. eBPF Hardware Offload to SmartNICs: cls_bpf and XDP. Proceedings of netdev, 1 (2016).

[23]

Sakari Lahti, Panu Sjövall, Jarno Vanne, and Timo D Hämäläinen. 2018. Are we there yet? A study on the state of high-level synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 38, 5 (2018), 898–911.

[24]

Leonardo Linguaglossa, Stanislav Lange, Salvatore Pontarelli, Gábor Rétvári, Dario Rossi, Thomas Zinner, Roberto Bifulco, Michael Jarschel, and Giuseppe Bianchi. 2019. Survey of Performance Acceleration Techniques for Network Function Virtualization. Proc. IEEE, 107, 4 (2019), 746–764. https://doi.org/10.1109/JPROC.2019.2896848

[25]

Devon Loehr and David Walker. 2022. Safe, Modular Packet Pipeline Programming. In Symposium on Principles of Programming Languages. 6.

[26]

Thomas Luinaud, Jeferson Santiago da Silva, JM Pierre Langlois, and Yvon Savaria. 2021. Design Principles for Packet Deparsers on FPGAs. In The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. 280–286.

[27]

Scott A Mahlke, Richard E Hank, James E McCormick, David I August, and Wen-Mei W Hwu. 1995. A comparison of full and partial predicated execution support for ILP processors. In Proceedings of the 22nd annual international symposium on Computer architecture. 138–150.

Digital Library

[28]

Marvell. 2021. Marvell OCTEON 10 DPU Platform. https://www.marvell.com/content/dam/marvell/en/public-collateral/embedded-processors/marvell-octeon-10-dpu-platform-product-brief.pdf

[29]

Rui Miao, Hongyi Zeng, Changhoon Kim, Jeongkeun Lee, and Minlan Yu. 2017. SilkRoad: Making Stateful Layer-4 Load Balancing Fast and Cheap Using Switching ASICs. In Proceedings of the Conference of the ACM Special Interest Group on Data Communication (SIGCOMM ’17). Association for Computing Machinery, New York, NY, USA. 15–28. isbn:9781450346535 https://doi.org/10.1145/3098822.3098824

Digital Library

[30]

Razvan Nane, Vlad-Mihai Sima, Christian Pilato, Jongsok Choi, Blair Fort, Andrew Canis, Yu Ting Chen, Hsuan Hsiao, Stephen Brown, and Fabrizio Ferrandi. 2015. A survey and evaluation of FPGA high-level synthesis tools. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 35, 10 (2015), 1591–1604.

Digital Library

[31]

Napatech. 2023. Scaling Suricata Performance to 100 Gbps With Napatech SmartNICs. https://www.napatech.com/support/resources/solution-descriptions/scaling-suricata-performance-to-100-gbps-with-napatech-smartnics/

[32]

NEC. 2020. Building an Open vRAN Ecosystem White Paper. https://www.nec.com/en/global/solutions/5g/index.html

[33]

Nvidia. 2021. Nvidia Bluefield-2 DPU. https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/documents/datasheet-nvidia-bluefield-2-dpu.pdf

[34]

M Akif Özkan, Arsène Pérard-Gayot, Richard Membarth, Philipp Slusallek, Roland Leiß a, Sebastian Hack, Jürgen Teich, and Frank Hannig. 2020. AnyHLS: high-level synthesis with partial evaluation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39, 11 (2020), 3202–3214.

[35]

Pensando. 2022. Distributed Services Card. https://www.amd.com/system/files/documents/pensando-dsc-200-product-brief.pdf

[36]

Ben Pfaff, Justin Pettit, Teemu Koponen, Ethan Jackson, Andy Zhou, Jarno Rajahalme, Jesse Gross, Alex Wang, Joe Stringer, and Pravin Shelar. 2015. The design and implementation of Open vSwitch. In 12th USENIX Symposium on Networked Systems Design and Implementation (NSDI 15). 117–130.

Digital Library

[37]

Phitchaya Mangpo Phothilimthana, Ming Liu, Antoine Kaufmann, Simon Peter, Rastislav Bodik, and Thomas Anderson. 2018. Floem: A Programming System for $NIC-Accelerated$ Network Applications. In 13th USENIX Symposium on Operating Systems Design and Implementation (OSDI 18). 663–679.

[38]

Salvatore Pontarelli, Roberto Bifulco, Marco Bonola, Carmelo Cascone, Marco Spaziani, Valerio Bruschi, Davide Sanvito, Giuseppe Siracusano, Antonio Capone, and Michio Honda. 2019. Flowblaze: Stateful packet processing in hardware. In 16th USENIX Symposium on Networked Systems Design and Implementation (NSDI 19). 531–548.

[39]

Giuseppe Siracusano, Salvator Galea, Davide Sanvito, Mohammad Malekzadeh, Gianni Antichi, Paolo Costa, Hamed Haddadi, and Roberto Bifulco. 2022. Re-architecting Traffic Analysis with Neural Network Interface Cards. In 19th USENIX Symposium on Networked Systems Design and Implementation (NSDI 22). 513–533.

[40]

Anirudh Sivaraman, Alvin Cheung, Mihai Budiu, Changhoon Kim, Mohammad Alizadeh, Hari Balakrishnan, George Varghese, Nick McKeown, and Steve Licking. 2016. Packet transactions: High-level programming for line-rate switches. In Proceedings of the 2016 ACM SIGCOMM Conference. 15–28.

Digital Library

[41]

Suricata. 2023. Suricata IDS Website. https://suricata.io/

[42]

tomshardware.com. 2022. AMD Acquires Pensando Data Processing Units in a $1.9 Billion Deal. https://www.tomshardware.com/news/amd-acquires-pensando-data-processing-units

[43]

Han Wang, Robert Soulé, Huynh Tu Dang, Ki Suh Lee, Vishal Shrivastav, Nate Foster, and Hakim Weatherspoon. 2017. P4FPGA: A rapid prototyping framework for p4. In Proceedings of the Symposium on SDN Research. 122–135.

Digital Library

[44]

Xilinx. 2017. P4-SDNet User Guide. https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1252-p4-sdnet.pdf

[45]

Xilinx. 2021. Alveo SN1000 SmartNICs. https://www.xilinx.com/content/dam/xilinx/publications/product-briefs/xilinx-alveo-sn1000-product-brief.pdf

[46]

Xilinx. 2022. Introduction to Vitis HLS. https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/Introduction-to-Vitis-HLS

[47]

Noa Zilberman, Yury Audzevich, G Adam Covington, and Andrew W Moore. 2014. NetFPGA SUME: Toward 100 Gbps as research commodity. IEEE micro, 34, 5 (2014), 32–41.

[48]

Noa Zilberman, Gabi Bracha, and Golan Schzukin. 2019. Stardust: Divide and Conquer in the Data Center Network. In 16th USENIX Symposium on Networked Systems Design and Implementation (NSDI 19). USENIX Association, Boston, MA. 141–160. isbn:978-1-931971-49-2 https://www.usenix.org/conference/nsdi19/presentation/zilberman

Cited By

Azorin RMonterubbiano ACastellano GGallo MPontarelli SRossi D(2024)Taming the Elephants: Affordable Flow Length Prediction in the Data PlaneProceedings of the ACM on Networking10.1145/36494732:CoNEXT1(1-24)Online publication date: 28-Mar-2024
https://dl.acm.org/doi/10.1145/3649473
Mao JDing HZhai JMa STsafrir DMusuvathi MGupta RAbu-Ghazaleh N(2024)Merlin: Multi-tier Optimization of eBPF Code for Performance and CompactnessProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 310.1145/3620666.3651387(639-653)Online publication date: 27-Apr-2024
https://dl.acm.org/doi/10.1145/3620666.3651387
Rivitti ATulumello ABelocchi GBianchi G(2024)Decentralizing DDoS Protection via Efficient Hardware Offloading2024 IEEE 25th International Conference on High Performance Switching and Routing (HPSR)10.1109/HPSR62440.2024.10635987(49-54)Online publication date: 22-Jul-2024
https://doi.org/10.1109/HPSR62440.2024.10635987
Show More Cited By

Index Terms

eHDL: Turning eBPF/XDP Programs into Hardware Designs for the NIC
1. Hardware
  1. Electronic design automation
    1. Hardware description languages and compilation
2. Networks
  1. Network architectures
    1. Programming interfaces

Recommendations

P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs
FPGA '18: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

Packet parsing is a key step in SDN-aware devices. Packet parsers in SDN networks need to be both reconfigurable and fast, to support the evolving network protocols and the increasing multi-gigabit data rates. The combination of packet processing ...
DBHI: A Tool for Decoupled Functional Hardware-Software Co-Design on SoCs
FPGA '20: Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

This paper presents a system-level co-simulation and co-verification workflow to ease the transition from a software-only procedure, executed in a General Purpose processor, to the integration of a custom hardware accelerator developed in a Hardware ...
Hardware resource estimation for heterogeneous FPGA-based SoCs
SAC '17: Proceedings of the Symposium on Applied Computing

The increasing complexity of recent System-on-Chip (SoC) designs introduces new challenges for design space exploration tools. In addition to the time-to-market challenge, designers need to estimate rapidly and accurately both performance and area ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences

ASPLOS 2023: Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3

March 2023

820 pages

ISBN:9781450399180

DOI:10.1145/3582016

General Chair:
Tor M. Aamodt
University of British Columbia, Canada
,
Program Chairs:
Natalie Enright Jerger
University of Toronto, Canada
,
Michael Swift
University of Wisconsin-Madison, USA

Copyright © 2023 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

Sponsors

In-Cooperation

SIGBED: ACM Special Interest Group on Embedded Systems

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 25 March 2023

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Funding Sources

Horizon 2020 5GMED
EU - NGEU, NRRP MUR program, SERICS project

Conference

ASPLOS '23

Sponsor:

ASPLOS '23: 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3

March 25 - 29, 2023

BC, Vancouver, Canada

Acceptance Rates

Overall Acceptance Rate 535 of 2,713 submissions, 20%

Upcoming Conference

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

7
Total Citations
View Citations
708
Total Downloads

Downloads (Last 12 months)314
Downloads (Last 6 weeks)34

Reflects downloads up to 20 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

Azorin RMonterubbiano ACastellano GGallo MPontarelli SRossi D(2024)Taming the Elephants: Affordable Flow Length Prediction in the Data PlaneProceedings of the ACM on Networking10.1145/36494732:CoNEXT1(1-24)Online publication date: 28-Mar-2024
https://dl.acm.org/doi/10.1145/3649473
Mao JDing HZhai JMa STsafrir DMusuvathi MGupta RAbu-Ghazaleh N(2024)Merlin: Multi-tier Optimization of eBPF Code for Performance and CompactnessProceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 310.1145/3620666.3651387(639-653)Online publication date: 27-Apr-2024
https://dl.acm.org/doi/10.1145/3620666.3651387
Rivitti ATulumello ABelocchi GBianchi G(2024)Decentralizing DDoS Protection via Efficient Hardware Offloading2024 IEEE 25th International Conference on High Performance Switching and Routing (HPSR)10.1109/HPSR62440.2024.10635987(49-54)Online publication date: 22-Jul-2024
https://doi.org/10.1109/HPSR62440.2024.10635987
Feng MZhou JTang Y(2024)Enhancing Cloud-Native Security Through eBPF Technology2024 IEEE 11th International Conference on Cyber Security and Cloud Computing (CSCloud)10.1109/CSCloud62866.2024.00036(165-168)Online publication date: 28-Jun-2024
https://doi.org/10.1109/CSCloud62866.2024.00036
Ma YSmith SDai BFranke HSukhwani BAsaad SXiong JKindratenko VChen D(2024)UniNet: Accelerating the Container Network Data Plane in IaaS Clouds2024 IEEE 17th International Conference on Cloud Computing (CLOUD)10.1109/CLOUD62652.2024.00023(115-127)Online publication date: 7-Jul-2024
https://doi.org/10.1109/CLOUD62652.2024.00023
Pereira Gollnick JRanjan RJha D(2024)Defid: Detecting and Filtering Distributed Denial of Service Attack in Edge Computing Environment2024 International Conference on Artificial Intelligence of Things and Systems (AIoTSys)10.1109/AIoTSys63104.2024.10780564(1-6)Online publication date: 17-Oct-2024
https://doi.org/10.1109/AIoTSys63104.2024.10780564
Trivedi ABrunella MBaumann ACrooks NSchwarzkopf M(2023)CPU-free Computing: A Vision with a BlueprintProceedings of the 19th Workshop on Hot Topics in Operating Systems10.1145/3593856.3595906(1-14)Online publication date: 22-Jun-2023
https://dl.acm.org/doi/10.1145/3593856.3595906

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents