Standard cells are essential components of modern digital circuit designs. With process technologies advancing beyond the 5nm node, more routability issues have arisen due to the decreasing number of routing tracks, increasing number and complexity of design rules, and strict patterning rules. Automatic standard cell synthesis tools are struggling to design cells with severe routability issues. In this paper, we propose a routability-driven standard cell synthesis framework using a novel pin density aware congestion metric, lattice graph routability modelling approach, and dynamic external pin allocation methodology to generate routability optimized layouts. On a benchmark of 94 complex and hard-to-route standard cells, NVCell 2 improves the number of routable and LVS/DRC clean cell layouts by 84.0% and 87.2%, respectively. NVCell 2 can generate 98.9% of cells LVS/DRC clean, with 13.9% of the cells having smaller area, compared to an industrial standard cell library with over 1000 standard cells.

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Cited By

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Ma TFan GSun XLow KShao L(2025)Graph neural network based cell library characterization method for fast design technology co-optimizationIntegration10.1016/j.vlsi.2024.102316101(102316)Online publication date: Mar-2025
https://doi.org/10.1016/j.vlsi.2024.102316
Jiang YFang SDe V(2024)Concurrent Detailed Routing with Pin Pattern Re-generation for Ultimate Pin Access OptimizationProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3655918(1-6)Online publication date: 23-Jun-2024
https://dl.acm.org/doi/10.1145/3649329.3655918
Ho CRen H(2024)Large Language Model (LLM) for Standard Cell Layout Design Optimization2024 IEEE LLM Aided Design Workshop (LAD)10.1109/LAD62341.2024.10691722(1-6)Online publication date: 28-Jun-2024
https://doi.org/10.1109/LAD62341.2024.10691722

Index Terms

NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model
1. Computing methodologies
  1. Machine learning
2. Hardware
  1. Very large scale integration design
    1. Standard cell libraries

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Published In

ISPD '23: Proceedings of the 2023 International Symposium on Physical Design

March 2023

278 pages

ISBN:9781450399784

DOI:10.1145/3569052

General Chair:
David Chinnery
Siemens Digital Industries Software, USA
,
Program Chair:
Iris Hui-Ru Jiang
National Taiwan University, Taiwan

This work is licensed under a Creative Commons Attribution International 4.0 License.

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Association for Computing Machinery

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Published: 26 March 2023

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Ma TFan GSun XLow KShao L(2025)Graph neural network based cell library characterization method for fast design technology co-optimizationIntegration10.1016/j.vlsi.2024.102316101(102316)Online publication date: Mar-2025
https://doi.org/10.1016/j.vlsi.2024.102316
Jiang YFang SDe V(2024)Concurrent Detailed Routing with Pin Pattern Re-generation for Ultimate Pin Access OptimizationProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3655918(1-6)Online publication date: 23-Jun-2024
https://dl.acm.org/doi/10.1145/3649329.3655918
Ho CRen H(2024)Large Language Model (LLM) for Standard Cell Layout Design Optimization2024 IEEE LLM Aided Design Workshop (LAD)10.1109/LAD62341.2024.10691722(1-6)Online publication date: 28-Jun-2024
https://doi.org/10.1109/LAD62341.2024.10691722

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