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View all- Liu YXiong WWang JLai J(2024)A new model for parametrically evaluating the routability of GRM FPGAIEICE Electronics Express10.1587/elex.20.2023055621:3(20230556-20230556)Online publication date: 10-Feb-2024
We have developed a hop-based complete detailed router ROAD-HOP that uses the Bump & Refit (B&R) approach to route a FPGA circuit in a near-optimal manner. This approach is based on generating a minimum-spanning tree (MST) from the complete pin-to-pin ...
The advances of FPGA technology and increasing size of FPGA designs pose great challenges on FPGA design tools. Deep research on FPGA physical design problems is paramount to improve industrial tools. This contest is the first ISPD contest on FPGA CAD ...
FPGA packing and placement without routability consideration could lead to unroutable results for high-utilization designs. Conventional FPGA packing and placement approaches are shown to have severe difficulties to yield good routability. In this paper, ...
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