Automatic equivalence check of circuit descriptions at clocked algorithmic and register transfer level (poster paper)

A multivalued flip-flop is presented. The implementation of the flip-flop is independent of N (number of logic levels). The output of the flip-flop is stable during clock transitions. Techniques in the design of sequential circuits using this type of ...

This paper presents a CMOS circuit methodology for designing pipeline stages which are both faster than comparable domino based stages and that also have increased functional capability. The basic gates offer considerably faster switching speeds than ...

Retiming is a powerful technique for optimizing sequential circuits. The transparent nature of level sensitive latches enables level-clocked circuits to operate faster and require fewer memory elements than edge-triggered circuits. However, this ...