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Automatic lighthouse generation for directed state space search

Published: 01 January 2000 Publication History
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References

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B. Chen, M. Yamazaki, and M. Fujita. Bug Identification of a Real Chip Design by Symbolic Model Checking. In Proc. European Conf. on Design Automation, pages 132-136, March 1994.
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M. Ganai, A. Aziz, and A. Kuehlmann. Enhancing Simulation with BDDs and ATPG. In Proc. of the Design Automation Conf., New Orleans, LA, June 1999.
[3]
E Goel. An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits. IEEE Transactions on Computers, C-31:215-222, 1981.
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Kenneth L. McMillan. Symbolic Model Checking. K- luwer Academic Publishers, 1993.
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J. Silva and K. Sakallah. GRASP-A New Search Algorithm For Satisfiability. In Proc. Intl. Conf. on Computer-Aided Design, Santa Clara, CA, November 1996.

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      cover image ACM Conferences
      DATE '00: Proceedings of the conference on Design, automation and test in Europe
      January 2000
      707 pages
      ISBN:1581132441
      DOI:10.1145/343647
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      • EDAA: European Design Automation Association
      • ECSI
      • EDAC: Electronic Design Automation Consortium
      • SIGDA: ACM Special Interest Group on Design Automation
      • IEEE-CS: Computer Society
      • IFIP: International Federation for Information Processing
      • The Russian Academy of Sciences: The Russian Academy of Sciences

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      Association for Computing Machinery

      New York, NY, United States

      Publication History

      Published: 01 January 2000

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      DATE00
      Sponsor:
      • EDAA
      • EDAC
      • SIGDA
      • IEEE-CS
      • IFIP
      • The Russian Academy of Sciences
      DATE00: Design Automation and Test in Europe
      March 27 - 30, 2000
      Paris, France

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      Overall Acceptance Rate 518 of 1,794 submissions, 29%

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      March 31 - April 2, 2025
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      • (2007)Hybrid Verification of Protocol BridgesIEEE Design & Test10.1109/MDT.2007.4724:2(124-131)Online publication date: 1-Mar-2007
      • (2007)A Survey of Hybrid Techniques for Functional VerificationIEEE Design & Test10.1109/MDT.2007.3024:2(112-122)Online publication date: 1-Mar-2007
      • (2006)Distance-guided hybrid verification with GUIDOProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131816(1211-1216)Online publication date: 6-Mar-2006
      • (2006)Distance-Guided Hybrid Verification with GUIDOProceedings of the Design Automation & Test in Europe Conference10.1109/DATE.2006.244050(1-6)Online publication date: 2006
      • (2003)Efficient Hybrid Reachability Analysis for Asynchronous Concurrent SystemsCorrect Hardware Design and Verification Methods10.1007/978-3-540-39724-3_33(378-393)Online publication date: 2003
      • (2001)Rarity based guided state space searchProceedings of the 11th Great Lakes symposium on VLSI10.1145/368122.368878(97-102)Online publication date: 1-Mar-2001

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