Analytical modeling of NoCs for fast simulation and design exploration (invited)

Networks-On-Chip are widely used in modern System-on-Chips to provide necessary communication between growing number of IP blocks. They are paramount to performance and power as they constitute primary shared resources in the systems. Modern system-level simulators and design exploration tools integrate cycle-accurate models of the NoCs which are notoriously slow and therefore severely impact the design process. To maintain design agility, there is a need for scalable, fast, and accurate simulation and design exploration frameworks. In this talk I will discuss recent research on the fast and accurate analytical models that can replace slow cycle-accurate models of the NoCs in system-level models. This research leverages queuing theory for quick automatic generation of the analytical models for systems with many traffic classes, priority arbitration and bursty traffic. I will conclude with future research directions.