[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ skip to main content
10.1145/3489517.3530413acmconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
research-article

PathFinder: side channel protection through automatic leaky paths identification and obfuscation

Published: 23 August 2022 Publication History

Abstract

Side-channel analysis (SCA) attacks show an enormous threat to cryptographic integrated circuits (ICs). To address this threat, designers try to adopt various countermeasures during the IC development process. However, many existing solutions are costly in terms of area, power and/or performance, and may require full-custom circuit design for proper implementations. In this paper, we propose a tool, namely PathFinder, to automatically identify leaky paths and protect the design, and is compatible with the commercial design flow. The tool first finds out partial logic cells that leak the most information through dynamic correlation analysis. PathFinder then exploits static security checking to construct complete leaky paths based on these cells. After leaky paths are identified, PathFinder will leverage proper hardware countermeasures, including Boolean masking and random precharge, to eliminate information leakage from these paths. The effectiveness of PathFinder is validated both through simulation and physical measurements on FPGA implementations. Results demonstrate more than 1000X improvements on side-channel resistance, with less than 6.53% penalty to the power, area and performance.

References

[1]
P. Kocher, J. Jaffe, and B. Jun, "Differential power analysis," in Annual International Cryptology Conference. Springer, 1999, pp. 388--397.
[2]
A. Moradi, A. Poschmann, S. Ling, C. Paar, and H. Wang, "Pushing the limits: A very compact and a threshold implementation of AES," in Annual International Conference on the Theory and Applications of Cryptographic Techniques. Springer, 2011, pp. 69--88.
[3]
M. A. KF, V. Ganesan, R. Bodduna, and C. Rebeiro, "PARAM: A microprocessor hardened for power side-channel attack resistance," in 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST). IEEE, 2020, pp. 23--34.
[4]
Y. Yao, T. Kathuria, B. Ege, and P. Schaumont, "Architecture correlation analysis (ACA): identifying the source of side-channel leakage at gate-level," in 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST). IEEE, 2020, pp. 188--196.
[5]
M. He, J. Park, A. Nahiyan, A. Vassilev, Y. Jin, and M. Tehranipoor, "RTL-PSC: Automated power side-channel leakage assessment at register-transfer level," in Proceedings of the 37th IEEE VLSI Test Symposium (VTS). Monterey, CA, USA: IEEE, 2019, pp. 1--6.
[6]
D. Sijacic, J. Balasch, B. Yang, S. Ghosh, and I. Verbauwhede, "Towards efficient and automated side channel evaluations at design time," Kalpa Publications in Computing, pp. 16--31, 2018.
[7]
X. Wang, W. Yueh, D. B. Roy, S. Narasimhan, Y. Zheng, S. Mukhopadhyay, D. Mukhopadhyay, and S. Bhunia, "Role of power grid in side channel attack and power-grid-aware secure design," in Proceedings of the 50th Annual Design Automation Conference. ACM, 2013, p. 78.
[8]
A. Singh, M. Kar, V. C. K. Chekuri, S. K. Mathew, A. Rajan, V. De, and S. Mukhopadhyay, "Enhanced power and electromagnetic SCA resistance of encryption engines via a security-aware integrated all-digital ldo," IEEE Journal of Solid-State Circuits, vol. 55, no. 2, pp. 478--493, 2019.
[9]
D. Das, J. Danial, A. Golder, N. Modak, S. Maity, B. Chatterjee, D. Seo, M. Chang, A. Varna, H. Krishnamurthy et al., "27.3 EM and power SCA-resilient AES-256 in 65nm cmos through > 350X current-domain signature attenuation," in 2020 IEEE International Solid-State Circuits Conference-(ISSCC). IEEE, 2020, pp. 424--426.
[10]
A. R. Shahmirzadi and A. Moradi, "Re-consolidating first-order masking schemes," IACR Transactions on Cryptographic Hardware and Embedded Systems, pp. 305--342, 2021.
[11]
P. Slpsk, P. K. Vairam, C. Rebeiro, and V. Kamakoti, "Karna: A gate-sizing based security aware EDA flow for improved power side-channel attack protection," in 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 2019, pp. 1--8.
[12]
D. Das, M. Nath, B. Chatterjee, S. Ghosh, and S. Sen, "STELLAR: A generic EM side-channel attack protection through ground-up root-cause analysis," in 2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST). IEEE, 2019, pp. 11--20.

Cited By

View all
  • (2024)SCAR: Power Side-Channel Analysis at RTL LevelIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2024.339060132:6(1110-1123)Online publication date: Jun-2024
  • (2023)Challenges and Opportunities of Security-Aware EDAACM Transactions on Embedded Computing Systems10.1145/357619922:3(1-34)Online publication date: 19-Apr-2023

Recommendations

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences
DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference
July 2022
1462 pages
ISBN:9781450391429
DOI:10.1145/3489517
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 23 August 2022

Permissions

Request permissions for this article.

Check for updates

Author Tags

  1. CAD for security
  2. countermeasure
  3. side channel analysis

Qualifiers

  • Research-article

Funding Sources

Conference

DAC '22
Sponsor:
DAC '22: 59th ACM/IEEE Design Automation Conference
July 10 - 14, 2022
California, San Francisco

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25
62nd ACM/IEEE Design Automation Conference
June 22 - 26, 2025
San Francisco , CA , USA

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)95
  • Downloads (Last 6 weeks)7
Reflects downloads up to 13 Dec 2024

Other Metrics

Citations

Cited By

View all
  • (2024)SCAR: Power Side-Channel Analysis at RTL LevelIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2024.339060132:6(1110-1123)Online publication date: Jun-2024
  • (2023)Challenges and Opportunities of Security-Aware EDAACM Transactions on Embedded Computing Systems10.1145/357619922:3(1-34)Online publication date: 19-Apr-2023

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media