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Towards a Truly Integrated Vector Processing Unit for Memory-bound Applications Based on a Cost-competitive Computational SRAM Design Solution

Authors:

Antoine Heraud,

Henri-Pierre Charles,

Bastien Giraud,

Valentin Egloff,

Jean-Philippe NoelAuthors Info & Claims

ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 18, Issue 2

Article No.: 40, Pages 1 - 26

https://doi.org/10.1145/3485823

Published: 28 April 2022 Publication History

Abstract

This article presents Computational SRAM (C-SRAM) solution combining In- and Near-Memory Computing approaches. It allows performing arithmetic, logic, and complex memory operations inside or next to the memory without transferring data over the system bus, leading to significant energy reduction. Operations are performed on large vectors of data occupying the entire physical row of C-SRAM array, leading to high performance gains. We introduce the C-SRAM solution in this article as an integrated vector processing unit to be used by a scalar processor as an energy-efficient and high performing co-processor. We detail the C-SRAM system design on different levels: (i) circuit design and silicon proof of concept, (ii) system interface and instruction set architecture, and (iii) high-level software programming and simulation. Experimental results on two complete memory-bound applications, AES and MobileNetV2, show that the C-SRAM implementation achieves up to 70× timing speedup and 37× energy reduction compared to scalar architecture, and up to 17× timing speedup and 5× energy reduction compared to SIMD architecture.

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Cited By

De La Fuente LChristmann JPezzin MRemars MSentieys O(2024)A Hardware Instruction Generation Mechanism for Energy-Efficient Computational Memories2024 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS58744.2024.10557870(1-5)Online publication date: 19-May-2024
https://doi.org/10.1109/ISCAS58744.2024.10557870
Matrangolo PMarchand CNavarro DO’Connor IBosio A(2024)Emerging Technologies for Memory-Centric ComputingDesign and Applications of Emerging Computer Systems10.1007/978-3-031-42478-6_1(3-29)Online publication date: 14-Jan-2024
https://doi.org/10.1007/978-3-031-42478-6_1
Marchand CNicolas AMatrangolo PNavarro DBosio AO’Connor I(2023)FeFET based Logic-in-Memory design methodologies, tools and open challenges2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC57769.2023.10321901(1-6)Online publication date: 16-Oct-2023
https://doi.org/10.1109/VLSI-SoC57769.2023.10321901
Show More Cited By

Index Terms

Towards a Truly Integrated Vector Processing Unit for Memory-bound Applications Based on a Cost-competitive Computational SRAM Design Solution
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Heterogeneous (hybrid) systems
    2. Parallel architectures
      1. Single instruction, multiple data
  2. Dependable and fault-tolerant systems and networks
    1. Processors and memory architectures
2. Hardware

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Information & Contributors

Information

Published In

cover image ACM Journal on Emerging Technologies in Computing Systems

ACM Journal on Emerging Technologies in Computing Systems Volume 18, Issue 2

April 2022

411 pages

ISSN:1550-4832

EISSN:1550-4840

DOI:10.1145/3508462

Editor:
Ramesh Karri
Polytechnic Institute of New York University, USA

Issue’s Table of Contents

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 28 April 2022

Accepted: 01 September 2021

Received: 01 September 2020

Published in JETC Volume 18, Issue 2

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Cited By

De La Fuente LChristmann JPezzin MRemars MSentieys O(2024)A Hardware Instruction Generation Mechanism for Energy-Efficient Computational Memories2024 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS58744.2024.10557870(1-5)Online publication date: 19-May-2024
https://doi.org/10.1109/ISCAS58744.2024.10557870
Matrangolo PMarchand CNavarro DO’Connor IBosio A(2024)Emerging Technologies for Memory-Centric ComputingDesign and Applications of Emerging Computer Systems10.1007/978-3-031-42478-6_1(3-29)Online publication date: 14-Jan-2024
https://doi.org/10.1007/978-3-031-42478-6_1
Marchand CNicolas AMatrangolo PNavarro DBosio AO’Connor I(2023)FeFET based Logic-in-Memory design methodologies, tools and open challenges2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC57769.2023.10321901(1-6)Online publication date: 16-Oct-2023
https://doi.org/10.1109/VLSI-SoC57769.2023.10321901
Noel JValea EGrenouillet LChapuis BFisher CRecoquillay AGiraud B(2023)Compute-In-Place Serial FeRAM: Enhancing Performance, Efficiency and Adaptability in Critical Embedded Systems2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC57769.2023.10321864(1-6)Online publication date: 16-Oct-2023
https://doi.org/10.1109/VLSI-SoC57769.2023.10321864
Golden CIlan DHuang CZhang NZhang ZBatten C(2023)Supporting a Virtual Vector Instruction Set on a Commercial Compute-in-SRAM AcceleratorIEEE Computer Architecture Letters10.1109/LCA.2023.3341389(1-4)Online publication date: 2023
https://doi.org/10.1109/LCA.2023.3341389

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