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Towards Better Standard Cell Library: Optimizing Compound Logic Gates for TFHE

Published: 15 November 2021 Publication History

Abstract

In this paper, we cryptographically optimize the constructions of3-input gates or multi-output gates using Fully Homomorphic Encryption (FHE) including Half Adder, Full Adder and AOI21. We implemented the gates over Torus Fully Homomorphic Encryption(TFHE). These gates achieve their respective functionalities with less computational cost than conventional constructions. By using the proposed gates, 16-bit adders and 16-bit multipliers can be evaluated about 5× and 2.5× faster, respectively, compared to the conventional constructions.

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  • (2024)Improved homomorphic evaluation for hash function based on TFHECybersecurity10.1186/s42400-024-00204-07:1Online publication date: 2-Jul-2024
  • (2024)AutoHoG: Automating Homomorphic Gate Design for Large-Scale Logic Circuit EvaluationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.335759843:7(1971-1983)Online publication date: Jul-2024
  • (2024)UFC: A Unified Accelerator for Fully Homomorphic Encryption2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO61859.2024.00034(352-365)Online publication date: 2-Nov-2024
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  1. Towards Better Standard Cell Library: Optimizing Compound Logic Gates for TFHE

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    cover image ACM Conferences
    WAHC '21: Proceedings of the 9th on Workshop on Encrypted Computing & Applied Homomorphic Cryptography
    November 2021
    75 pages
    ISBN:9781450386562
    DOI:10.1145/3474366
    This work is licensed under a Creative Commons Attribution International 4.0 License.

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    New York, NY, United States

    Publication History

    Published: 15 November 2021

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    Author Tags

    1. full adder
    2. logic circuits
    3. tfhe

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    View all
    • (2024)Improved homomorphic evaluation for hash function based on TFHECybersecurity10.1186/s42400-024-00204-07:1Online publication date: 2-Jul-2024
    • (2024)AutoHoG: Automating Homomorphic Gate Design for Large-Scale Logic Circuit EvaluationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.335759843:7(1971-1983)Online publication date: Jul-2024
    • (2024)UFC: A Unified Accelerator for Fully Homomorphic Encryption2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)10.1109/MICRO61859.2024.00034(352-365)Online publication date: 2-Nov-2024
    • (2023)Enhancing the Privacy of Machine Learning via faster arithmetic over Torus FHE2023 IEEE 10th International Conference on Cyber Security and Cloud Computing (CSCloud)/2023 IEEE 9th International Conference on Edge Computing and Scalable Cloud (EdgeCom)10.1109/CSCloud-EdgeCom58631.2023.00017(46-52)Online publication date: Jul-2023
    • (2022)Privacy-Preserving Feature Selection with Fully Homomorphic EncryptionAlgorithms10.3390/a1507022915:7(229)Online publication date: 30-Jun-2022
    • (2022)Efficient Hardware Implementations of Legendre Symbol Suitable for MPC ApplicationsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2021.313277069:3(1231-1239)Online publication date: Mar-2022
    • (2022)High-Speed Post-Quantum Cryptoprocessor Based on RISC-V Architecture for IoTIEEE Internet of Things Journal10.1109/JIOT.2022.31528509:17(15839-15846)Online publication date: 1-Sep-2022

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