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DHOOM: Reusing Design-for-Debug Hardware for Online Monitoring

Published: 02 June 2019 Publication History

Abstract

Runtime verification employs dedicated hardware or software monitors to check whether program properties hold at runtime. However, these monitors often incur high area and performance overheads depending on whether they are implemented in hardware or software. In this work, we propose DHOOM, an architectural framework for runtime monitoring of program assertions, which exploits the combination of a reconfigurable fabric present alongside a processor core with the vestigial on-chip Design-for-Debug hardware. This combination of hardware features allows DHOOM to minimize the overall performance overhead of runtime verification, even when subject to a given area constraint. We present an algorithm for dynamically selecting an effective subset of assertion monitors that can be accommodated in the available programmable fabric, while instrumenting the remaining assertions in software. We show that our proposed strategy, while respecting area constraints, reduces the performance overhead of runtime verification by up to 32% when compared with a baseline of software-only monitors.

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Cited By

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  • (2024)faRM-LTL: A Domain-Specific Architecture for Flexible and Accelerated Runtime Monitoring of LTL PropertiesRuntime Verification10.1007/978-3-031-74234-7_7(109-127)Online publication date: 12-Oct-2024
  • (2023) ReDeSIGN: Re use of De bug S tructures for I mprovement in Performance G ain of N oC Based MPSoCs IEEE Transactions on Emerging Topics in Computing10.1109/TETC.2022.320361111:2(432-447)Online publication date: 1-Apr-2023
  • (2021)Opportunistic Caching in NoC: Exploring Ways to Reduce Miss PenaltyIEEE Transactions on Computers10.1109/TC.2021.306996870:6(892-905)Online publication date: 1-Jun-2021

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Published In

cover image ACM Conferences
DAC '19: Proceedings of the 56th Annual Design Automation Conference 2019
June 2019
1378 pages
ISBN:9781450367257
DOI:10.1145/3316781
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 02 June 2019

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Author Tags

  1. Design-for-Debug Hardware
  2. Runtime Monitoring

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all
  • (2024)faRM-LTL: A Domain-Specific Architecture for Flexible and Accelerated Runtime Monitoring of LTL PropertiesRuntime Verification10.1007/978-3-031-74234-7_7(109-127)Online publication date: 12-Oct-2024
  • (2023) ReDeSIGN: Re use of De bug S tructures for I mprovement in Performance G ain of N oC Based MPSoCs IEEE Transactions on Emerging Topics in Computing10.1109/TETC.2022.320361111:2(432-447)Online publication date: 1-Apr-2023
  • (2021)Opportunistic Caching in NoC: Exploring Ways to Reduce Miss PenaltyIEEE Transactions on Computers10.1109/TC.2021.306996870:6(892-905)Online publication date: 1-Jun-2021
  • (2020)A Formal Approach to Accountability in Heterogeneous Systems-on-ChipIEEE Transactions on Dependable and Secure Computing10.1109/TDSC.2020.2970417(1-1)Online publication date: 2020

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