research-article

Cache-Aware Dynamic Skewed Tree for Fast Memory Authentication

Authors:

Saru Vig,

Siew-Kei Lam,

Rohan JunejaAuthors Info & Claims

ASPDAC '21: Proceedings of the 26th Asia and South Pacific Design Automation Conference

Pages 402 - 407

https://doi.org/10.1145/3394885.3431593

Published: 29 January 2021 Publication History

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Abstract

Memory integrity trees are widely-used to protect external memories in embedded systems against bus attacks. However, existing methods often result in high performance overheads incurred during memory authentication. To reduce memory accesses during authentication, the tree nodes are cached on-chip. In this paper, we propose a cacheaware technique to dynamically skew the integrity tree based on the application workloads in order to reduce the performance overhead. The tree is initialized using Van-Emde Boas (vEB) organization to take advantage of locality of reference. At run time, the nodes of the integrity tree are dynamically positioned based on their memory access patterns. In particular, frequently accessed nodes are placed closer to the root to reduce the memory access overheads. The proposed technique is compared with existing methods on Multi2Sim using benchmarks from SPEC-CPU2006, SPLASH-2 and PARSEC to demonstrate its performance benefits.

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Saru Vig, Rohan Juneja, Guiyuan Jiang, Siew-Kei Lam, and Changhai Ou. 2019. Framework for Fast Memory Authentication Using Dynamically Skewed Integrity Tree. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27, 10 (2019), 2331--2343.

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Cited By

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Zou YZubair KAlwadi MShadab RGandham SAwad ALin M(2022)ARES: Persistently Secure Non-Volatile Memory with Processor-transparent and Hardware-friendly Integrity Verification and Metadata RecoveryACM Transactions on Embedded Computing Systems10.1145/349273521:1(1-32)Online publication date: 10-Feb-2022
https://dl.acm.org/doi/10.1145/3492735

Index Terms

Cache-Aware Dynamic Skewed Tree for Fast Memory Authentication
1. Security and privacy
  1. Security in hardware
    1. Hardware security implementation
      1. Hardware-based security protocols

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Published In

ASPDAC '21: Proceedings of the 26th Asia and South Pacific Design Automation Conference

January 2021

930 pages

ISBN:9781450379991

DOI:10.1145/3394885

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 29 January 2021

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ASPDAC '21

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SIGDA

ASPDAC '21: 26th Asia and South Pacific Design Automation Conference

January 18 - 21, 2021

Tokyo, Japan

Acceptance Rates

ASPDAC '21 Paper Acceptance Rate 111 of 368 submissions, 30%;

Overall Acceptance Rate 466 of 1,454 submissions, 32%

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ASPDAC '25

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30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

Tokyo , Japan

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Zou YZubair KAlwadi MShadab RGandham SAwad ALin M(2022)ARES: Persistently Secure Non-Volatile Memory with Processor-transparent and Hardware-friendly Integrity Verification and Metadata RecoveryACM Transactions on Embedded Computing Systems10.1145/349273521:1(1-32)Online publication date: 10-Feb-2022
https://dl.acm.org/doi/10.1145/3492735

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Recommendations

Reusability-aware cache memory sharing for chip multiprocessors with private L2 caches

Criticality aware tiered cache hierarchy: a fundamental relook at multi-level cache hierarchies

Capturing dynamic memory reference behavior with adaptive cache topology