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Aging-Aware Request Scheduling for Non-Volatile Main Memory

Authors:

Nagarajan KandasamyAuthors Info & Claims

ASPDAC '21: Proceedings of the 26th Asia and South Pacific Design Automation Conference

Pages 657 - 664

https://doi.org/10.1145/3394885.3431529

Published: 29 January 2021 Publication History

Abstract

Modern computing systems are embracing non-volatile memory (NVM) to implement high-capacity and low-cost main memory. Elevated operating voltages of NVM accelerate the aging of CMOS transistors in the peripheral circuitry of each memory bank. Aggressive device scaling increases power density and temperature, which further accelerates aging, challenging the reliable operation of NVM-based main memory. We propose HEBE, an architectural technique to mitigate the circuit aging-related problems of NVM-based main memory. HEBE is built on three contributions. First, we propose a new analytical model that can dynamically track the aging in the peripheral circuitry of each memory bank based on the bank's utilization. Second, we develop an intelligent memory request scheduler that exploits this aging model at run time to de-stress the peripheral circuitry of a memory bank only when its aging exceeds a critical threshold. Third, we introduce an isolation transistor to decouple parts of a peripheral circuit operating at different voltages, allowing the decoupled logic blocks to undergo long-latency de-stress operations independently and off the critical path of memory read and write accesses, improving performance. We evaluate HEBE with workloads from the SPEC CPU2017 Benchmark suite. Our results show that HEBE significantly improves both performance and lifetime of NVM-based main memory.

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cover image ACM Conferences

ASPDAC '21: Proceedings of the 26th Asia and South Pacific Design Automation Conference

January 2021

930 pages

ISBN:9781450379991

DOI:10.1145/3394885

Copyright © 2021 ACM.

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Published: 29 January 2021

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ASPDAC '21: 26th Asia and South Pacific Design Automation Conference

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ASPDAC '21 Paper Acceptance Rate 111 of 368 submissions, 30%;

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Cited By

Kargar SNawab F(2023)Hamming Tree: The Case for Energy-Aware Indexing for NVMsProceedings of the ACM on Management of Data10.1145/35893271:2(1-27)Online publication date: 20-Jun-2023
https://dl.acm.org/doi/10.1145/3589327
S AKapoor H(2023)AGRAS: Aging and memory request rate aware scheduler for PCM memories2023 24th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED57927.2023.10129369(1-8)Online publication date: 5-Apr-2023
https://doi.org/10.1109/ISQED57927.2023.10129369
Zhang JWang CZhu ZKline DJones AYang HWang Y(2023)Realizing Extreme Endurance Through Fault-aware Wear Leveling and Improved Tolerance2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071093(964-976)Online publication date: Feb-2023
https://doi.org/10.1109/HPCA56546.2023.10071093
Oliveira GGhose SGómez-Luna JBoroumand ASavery ARao SQazi SGrignou GThakur RShiu EMutlu O(2023)Extending Memory Capacity in Modern Consumer Systems With Emerging Non-Volatile Memory: Experimental Analysis and Characterization Using the Intel Optane SSDIEEE Access10.1109/ACCESS.2023.331788411(105843-105871)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3317884
Xu RSha EZhuge QSong YWang H(2023)Loop interchange and tiling for multi-dimensional loops to minimize write operations on NVMsJournal of Systems Architecture10.1016/j.sysarc.2022.102799135(102799)Online publication date: Feb-2023
https://doi.org/10.1016/j.sysarc.2022.102799
Song SBalaji ADas AKandasamy N(2022)Design-Technology Co-Optimization for NVM-Based Neuromorphic Processing ElementsACM Transactions on Embedded Computing Systems10.1145/352406821:6(1-27)Online publication date: 12-Dec-2022
https://dl.acm.org/doi/10.1145/3524068
Song SChong HBalaji ADas AShackleford JKandasamy N(2022)DFSynthesizer: Dataflow-based Synthesis of Spiking Neural Networks to Neuromorphic HardwareACM Transactions on Embedded Computing Systems10.1145/347915621:3(1-35)Online publication date: 28-May-2022
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Xu RSha EZhuge QSong YLin JWang T(2022)Optimal Loop Tiling for Minimizing Write Operations on NVMs with Complete Memory Latency HidingProceedings of the 27th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC52403.2022.9712532(389-394)Online publication date: 17-Jan-2022
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Kargar SNawab F(2022)Challenges and future directions for energy, latency, and lifetime improvements in NVMsDistributed and Parallel Databases10.1007/s10619-022-07421-x41:3(163-189)Online publication date: 21-Sep-2022
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Ali JMaqsood TKhalid NMadani S(2022)Communication and aging aware application mapping for multicore based edge computing serversCluster Computing10.1007/s10586-022-03588-126:1(223-235)Online publication date: 30-Mar-2022
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