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research-article

VTR 8: High-performance CAD and Customizable FPGA Architecture Modelling

Authors:

Kevin E. Murray,

Mohamed Eldafrawy,

Jean-Philippe Legault,

Aaron G. Graham,

Matthew J. P. Walker,

Panagiotis Patros,

Kenneth B. Kent,

Vaughn BetzAuthors Info & Claims

ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 13, Issue 2

Article No.: 9, Pages 1 - 55

https://doi.org/10.1145/3388617

Published: 01 June 2020 Publication History

Abstract

Developing Field-programmable Gate Array (FPGA) architectures is challenging due to the competing requirements of various application domains and changing manufacturing process technology. This is compounded by the difficulty of fairly evaluating FPGA architectural choices, which requires sophisticated high-quality Computer Aided Design (CAD) tools to target each potential architecture. This article describes version 8.0 of the open source Verilog to Routing (VTR) project, which provides such a design flow. VTR 8 expands the scope of FPGA architectures that can be modelled, allowing VTR to target and model many details of both commercial and proposed FPGA architectures. The VTR design flow also serves as a baseline for evaluating new CAD algorithms. It is therefore important, for both CAD algorithm comparisons and the validity of architectural conclusions, that VTR produce high-quality circuit implementations. VTR 8 significantly improves optimization quality (reductions of 15% minimum routable channel width, 41% wirelength, and 12% critical path delay), run-time (5.3× faster) and memory footprint (3.3× lower). Finally, we demonstrate VTR is run-time and memory footprint efficient, while producing circuit implementations of reasonable quality compared to highly-tuned architecture-specific industrial tools—showing that architecture generality, good implementation quality, and run-time efficiency are not mutually exclusive goals.

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Cited By

Coulon LRamirez LAnderson JStojilović MIenne PPutnam ALi J(2025)FRIDA: Reconfigurable Arrays for Dynamically Scheduled High-Level SynthesisProceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays10.1145/3706628.3708880(147-158)Online publication date: 27-Feb-2025
https://dl.acm.org/doi/10.1145/3706628.3708880
Taka EHuang NChang CWu KArora AMarculescu DPutnam ALi J(2025)Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI AccelerationProceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays10.1145/3706628.3708867(159-171)Online publication date: 27-Feb-2025
https://dl.acm.org/doi/10.1145/3706628.3708867
Zhu JZuo DMa YNakamura YWang Y(2025)A Holistic FPGA Architecture Exploration Framework for Deep Learning AccelerationProceedings of the 30th Asia and South Pacific Design Automation Conference10.1145/3658617.3697698(1048-1054)Online publication date: 20-Jan-2025
https://dl.acm.org/doi/10.1145/3658617.3697698
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Index Terms

VTR 8: High-performance CAD and Customizable FPGA Architecture Modelling
1. Hardware
  1. Electronic design automation
  2. Integrated circuits
    1. Reconfigurable logic and FPGAs

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Published In

cover image ACM Transactions on Reconfigurable Technology and Systems

ACM Transactions on Reconfigurable Technology and Systems Volume 13, Issue 2

June 2020

185 pages

ISSN:1936-7406

EISSN:1936-7414

DOI:10.1145/3383521

Editor:
Deming Chen
University of Illinois, Urbana-Champaign Urbana

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Copyright © 2020 ACM.

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Publication History

Published: 01 June 2020

Online AM: 07 May 2020

Accepted: 01 March 2020

Revised: 01 January 2020

Received: 01 July 2019

Published in TRETS Volume 13, Issue 2

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Semiconductor Research Corporation
Lattice Semiconductor
New Brunswick Innovation Foundation
Canadian Foundation for Innovation
NSERC CGS-D scholarship
NSERC/Intel Industrial Research Chair in Programmable Silicon, Huawei
Ontario Graduate Scholarship

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https://dl.acm.org/doi/10.1145/3706628.3708880
Taka EHuang NChang CWu KArora AMarculescu DPutnam ALi J(2025)Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI AccelerationProceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays10.1145/3706628.3708867(159-171)Online publication date: 27-Feb-2025
https://dl.acm.org/doi/10.1145/3706628.3708867
Zhu JZuo DMa YNakamura YWang Y(2025)A Holistic FPGA Architecture Exploration Framework for Deep Learning AccelerationProceedings of the 30th Asia and South Pacific Design Automation Conference10.1145/3658617.3697698(1048-1054)Online publication date: 20-Jan-2025
https://dl.acm.org/doi/10.1145/3658617.3697698
Bhargav DPradyumna GRao M(2025)Meta-Heuristic Optimization of Custom Heterogeneous Blocks Defined eFPGA Design2025 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)10.1109/VLSID64188.2025.00069(326-331)Online publication date: 4-Jan-2025
https://doi.org/10.1109/VLSID64188.2025.00069
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Zhao MXiong YZhang HZheng HYu DShen Z(2025)CoaCAD: Correlation-Assisted Computer-Aided Design for Nonvolatile FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.341904844:1(144-156)Online publication date: 1-Jan-2025
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Nikolić SNikolić S(2025)Searching for Regular Switch-PatternsModern Programmable Interconnect Design10.1007/978-3-031-80629-2_6(175-202)Online publication date: 7-Mar-2025
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Nikolić SNikolić S(2025)Switch Presence NegotiationModern Programmable Interconnect Design10.1007/978-3-031-80629-2_5(121-174)Online publication date: 7-Mar-2025
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Nikolić SNikolić S(2025)Modeling Programmable Routing in Advanced TechnologiesModern Programmable Interconnect Design10.1007/978-3-031-80629-2_4(73-119)Online publication date: 7-Mar-2025
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