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Application-specific network-on-chip design space exploration framework for neuromorphic processor

Published: 23 May 2020 Publication History

Abstract

Neuromorphic processors can support the design of various Spiking Neural Networks (SNN) to deal with different tasks, such as recognition and tracking. Neuromorphic processors use Network-on-Chip (NoC) to support communication between neurons in SNN. The different SNN has different communication traffic patterns. It will pose the different challenges of the NoC designing. A reasonable NoC architecture can improve the overall performance such as lower latency of the processor. Hence, it is critical to implement the exploration of NoC architecture design for neuromorphic processors.
This paper proposes a rapid NoC design space exploration (DSE) framework. As to our knowledge, it is the first work for the NoC DSE for the neuromorphic processor. The framework takes the spikes of the SNN application as input. It can support multiple optimization objectives for NoC design. Meanwhile, an optimized simulated annealing algorithm has been used to perform the DSE for the NoC design space. Then it outputs the final NoC design configuration. We apply this framework to 7 SNN applications to perform the NoC DSE. Compared with baseline NoC configuration, the NoC DSE framework can improve performance (Average Transport latency) by 54% to 93%. Compared with the Simulated Annealing (SA) algorithm, the Better-History SA (BHSA) algorithm speeds up the searching process by 1.5 to 8 times.

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Cited By

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  • (2023)Back to Homogeneous Computing: A Tightly-Coupled Neuromorphic Processor With Neuromorphic ISAIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2023.330740834:11(2910-2927)Online publication date: Nov-2023
  • (2023)SNNOpt: An Application-Specific Design Framework for Spiking Neural Networks2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS)10.1109/AICAS57966.2023.10168605(1-5)Online publication date: 11-Jun-2023
  • (2023)Path-Based Multicast Routing for Network-on-Chip of the Neuromorphic ProcessorJournal of Computer Science and Technology10.1007/s11390-022-1232-838:5(1098-1112)Online publication date: 1-Sep-2023
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      cover image ACM Conferences
      CF '20: Proceedings of the 17th ACM International Conference on Computing Frontiers
      May 2020
      298 pages
      ISBN:9781450379564
      DOI:10.1145/3387902
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      Published: 23 May 2020

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      1. design space exploration
      2. network-on-chip
      3. neuromorphic processors
      4. simulated annealing
      5. spiking neural network

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      • National Key RD Program of China
      • National Natural Science Foundation of China
      • HGJ

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      May 11 - 13, 2020
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      View all
      • (2023)Back to Homogeneous Computing: A Tightly-Coupled Neuromorphic Processor With Neuromorphic ISAIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2023.330740834:11(2910-2927)Online publication date: Nov-2023
      • (2023)SNNOpt: An Application-Specific Design Framework for Spiking Neural Networks2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS)10.1109/AICAS57966.2023.10168605(1-5)Online publication date: 11-Jun-2023
      • (2023)Path-Based Multicast Routing for Network-on-Chip of the Neuromorphic ProcessorJournal of Computer Science and Technology10.1007/s11390-022-1232-838:5(1098-1112)Online publication date: 1-Sep-2023
      • (2022)DNAsim: Evaluation Framework for Digital Neuromorphic Architectures2022 25th Euromicro Conference on Digital System Design (DSD)10.1109/DSD57027.2022.00065(438-445)Online publication date: Aug-2022

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