Gate-Level Models for Fast Cross-Level Power Density Estimation
Pages 507 - 512
Abstract
We present a methodology for fast cycle-accurate gate-level power density analysis especially suited for hard macros. It leverages a post-PAR (place and route) design. The proposed model generation flow consists of three automated steps: partitioning the design into estimation regions, generating power models using gate-level simulation, estimating power dissipation and power density using a higher-level simulation engine (RTL or above). Our models are based on signal transition classification, which factors in the changes in circuit state caused by signal transitions, and corresponding lookup-tables. Our implementation shows a speedup of 320x for an open source processor (1800x for a multiplier) compared to a state-of-the-art commercial tool.
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References
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- Gate-Level Models for Fast Cross-Level Power Density Estimation
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Published In
September 2020
597 pages
ISBN:9781450379441
DOI:10.1145/3386263
- General Chairs:
- Tinoosh Mohsenin,
- Weisheng Zhao,
- Program Chairs:
- Yiran Chen,
- Onur Mutlu
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Association for Computing Machinery
New York, NY, United States
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Published: 07 September 2020
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