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A Global Routing Method for Graphene Nanoribbons Based Circuits and Interconnects

Authors:

Debesh Kumar Das,

Soumya PanditAuthors Info & Claims

ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 16, Issue 3

Article No.: 31, Pages 1 - 28

https://doi.org/10.1145/3384214

Published: 22 May 2020 Publication History

Abstract

With extreme miniaturization of traditional CMOS devices in deep sub-micron design levels, the delay of a circuit, as well as power dissipation and area are dominated by interconnections between logic blocks. Interconnect today is causing major problems such as delay, power dissipation, and so on. In an attempt to search for alternative materials, Graphene nanoribbons have been found to be potential for both transistors and interconnects due to its outstanding electrical and thermal properties. Graphene nanoribbons provide better options as materials used for global routing trees in VLSI circuits. However, certain special characteristics of Graphene nanoribbon prohibit direct application of existing VLSI routing tree construction methods. In this article, we address this issue and propose heuristic methods for construction of Graphene nanoribbon--based minimum hybrid cost and minimum-delay Steiner trees. We compute the delays for the trees using Elmore delay approximation. Experimental results demonstrate the effectiveness of our proposed methods, which are quite encouraging.

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Cited By

Yen CYan J(2023)Layer-Minimization-Oriented GNR Area Routing2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)10.1109/ICECS58634.2023.10382834(1-4)Online publication date: 4-Dec-2023
https://doi.org/10.1109/ICECS58634.2023.10382834
Das S Das D Pandit S(2023)A novel routing algorithm for GNR based interconnect considering area optimization, interconnect-reliability and timing issuesAnalog Integrated Circuits and Signal Processing10.1007/s10470-023-02170-y116:1-2(49-67)Online publication date: 1-Aug-2023
https://dl.acm.org/doi/10.1007/s10470-023-02170-y
Das SDas DPandit S(2023)Reduction of Interconnect Delay and Resistance While Minimizing Grid Area in GNR-Based VLSI Routing ProblemEmerging Electronic Devices, Circuits and Systems10.1007/978-981-99-0055-8_8(85-97)Online publication date: 1-May-2023
https://doi.org/10.1007/978-981-99-0055-8_8
Show More Cited By

Index Terms

A Global Routing Method for Graphene Nanoribbons Based Circuits and Interconnects
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Wire routing

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Published In

cover image ACM Journal on Emerging Technologies in Computing Systems

ACM Journal on Emerging Technologies in Computing Systems Volume 16, Issue 3

Special Issue on Nanoelectronic Device, Circuit, and Architecture Design, Part 1 and Regular Papers

July 2020

214 pages

ISSN:1550-4832

EISSN:1550-4840

DOI:10.1145/3399633

Editor:
Ramesh Karri
Polytechnic Institute of New York University, USA

Issue’s Table of Contents

Copyright © 2020 ACM.

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 22 May 2020

Online AM: 07 May 2020

Accepted: 01 February 2020

Revised: 01 December 2019

Received: 01 August 2018

Published in JETC Volume 16, Issue 3

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MeitY Government of India for supporting the research work carried out

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Cited By

Yen CYan J(2023)Layer-Minimization-Oriented GNR Area Routing2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)10.1109/ICECS58634.2023.10382834(1-4)Online publication date: 4-Dec-2023
https://doi.org/10.1109/ICECS58634.2023.10382834
Das S Das D Pandit S(2023)A novel routing algorithm for GNR based interconnect considering area optimization, interconnect-reliability and timing issuesAnalog Integrated Circuits and Signal Processing10.1007/s10470-023-02170-y116:1-2(49-67)Online publication date: 1-Aug-2023
https://dl.acm.org/doi/10.1007/s10470-023-02170-y
Das SDas DPandit S(2023)Reduction of Interconnect Delay and Resistance While Minimizing Grid Area in GNR-Based VLSI Routing ProblemEmerging Electronic Devices, Circuits and Systems10.1007/978-981-99-0055-8_8(85-97)Online publication date: 1-May-2023
https://doi.org/10.1007/978-981-99-0055-8_8
Das SDas DPandit S(2022)Reliability Aware Global Routing of Graphene Nanoribbon Based InterconnectVLSI Design and Test10.1007/978-3-031-21514-8_31(373-386)Online publication date: 17-Dec-2022
https://doi.org/10.1007/978-3-031-21514-8_31

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