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Design Rule Checking with a CNN Based Feature Extractor

Published: 16 November 2020 Publication History

Abstract

Design rule checking (DRC) is getting increasingly complex in advanced nodes technologies. It would be highly desirable to have a fast interactive DRC engine that could be used during layout. In this work, we establish the proof of feasibility for such an engine. The proposed model consists of a convolutional neural network (CNN) trained to detect DRC violations. The model was trained with artificial data that was derived from a set of 50 SRAM designs. The focus in this demonstration was metal 1 rules. Using this solution, we can detect multiple DRC violations 32x faster than Boolean checkers with an accuracy of up to 92%. The proposed solution can be easily expanded to a complete rule set.

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Cited By

View all
  • (2024)Performance Analysis of Different Processor Architectures Applied to CMP Process Modeling Acceleration2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617797(592-599)Online publication date: 10-May-2024
  • (2023)A Deep Transfer Learning Design Rule Checker With Synthetic TrainingIEEE Design & Test10.1109/MDAT.2022.316278640:1(77-84)Online publication date: Feb-2023
  • (2023)OpenDRC: An Efficient Open-Source Design Rule Checking Engine with Hierarchical GPU Acceleration2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247734(1-6)Online publication date: 9-Jul-2023
  • Show More Cited By

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Published In

cover image ACM Conferences
MLCAD '20: Proceedings of the 2020 ACM/IEEE Workshop on Machine Learning for CAD
November 2020
183 pages
ISBN:9781450375191
DOI:10.1145/3380446
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 16 November 2020

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Author Tags

  1. IC verification
  2. convolutional neural network
  3. deep learning
  4. design for manufacturing
  5. design rule checking
  6. machine learning

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  • Research-article

Funding Sources

  • CAEML IUCRC
  • National Science Foundation

Conference

MLCAD '20
Sponsor:
MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD
November 16 - 20, 2020
Virtual Event, Iceland

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Overall Acceptance Rate 35 of 83 submissions, 42%

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Cited By

View all
  • (2024)Performance Analysis of Different Processor Architectures Applied to CMP Process Modeling Acceleration2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10617797(592-599)Online publication date: 10-May-2024
  • (2023)A Deep Transfer Learning Design Rule Checker With Synthetic TrainingIEEE Design & Test10.1109/MDAT.2022.316278640:1(77-84)Online publication date: Feb-2023
  • (2023)OpenDRC: An Efficient Open-Source Design Rule Checking Engine with Hierarchical GPU Acceleration2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247734(1-6)Online publication date: 9-Jul-2023
  • (2023)Automated Design Rule Checker for VLSI Circuits Using Machine LearningVLSI, Communication and Signal Processing10.1007/978-981-99-0973-5_36(475-485)Online publication date: 2-Jul-2023
  • (2022)Challenges in Building Deployable Machine Learning Solutions for SoC Design2022 IEEE Women in Technology Conference (WINTECHCON)10.1109/WINTECHCON55229.2022.9832287(1-6)Online publication date: 2-Jun-2022
  • (2022)Machine Learning Approaches for Electronic Design Automation in IC Design Flow2022 Sixth International Conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC)10.1109/I-SMAC55078.2022.9987302(528-533)Online publication date: 10-Nov-2022
  • (2021)CNN based Design Rule Checker for VLSI Layouts2021 IEEE 2nd International Conference on Applied Electromagnetics, Signal Processing, & Communication (AESPC)10.1109/AESPC52704.2021.9708453(1-6)Online publication date: 26-Nov-2021

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