More Web Proxy on the site http://driver.im/

research-article

High-Performance FPGA Network Switch Architecture

Authors:

Philippos Papaphilippou,

Wayne LukAuthors Info & Claims

FPGA '20: Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

Pages 76 - 85

https://doi.org/10.1145/3373087.3375299

Published: 24 February 2020 Publication History

Abstract

We present a high-throughput FPGA design for supporting high-performance network switching. FPGAs have recently been attracting attention for datacenter computing due to their increasing transceiver count and capabilities, which also benefit the implementation and refinement of network switches. Our solution replaces the crossbar in favour of a novel, more pipeline-friendly approach, the "Combined parallel round-robin arbiter". It also removes the overhead of incorporating an often-iterative scheduling or matching algorithm, which sometimes tries to fit too many steps in a single or a few FPGA cycles. The result is a network switch implementation on FPGAs operating at a high frequency and with a low port-to-port latency. It also provides a wiser buffer memory utilisation than traditional Virtual Output Queue (VOQ)-based switches and is able to keep 100% throughput for a wider range of traffic patterns using a fraction of the buffer memory and shorter packets.

References

[1]

Mohamed S Abdelfattah, Andrew Bitar, and Vaughn Betz. 2015. Take the highway: Design for embedded NoCs on FPGAs. In Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. ACM, 98--107.

Digital Library

[2]

Thomas E Anderson, Susan S Owicki, James B Saxe, and Charles P Thacker. 1993. High-speed switch scheduling for local-area networks. ACM Transactions on Computer Systems (TOCS) 11, 4 (1993), 319--352.

Digital Library

[3]

Arista Networks, Inc. 2019. 7800R3 Series Data Center Switch Router Data Sheet.

[4]

Kenneth E Batcher. 1968. Sorting networks and their applications. In Proceedings of the April 30--May 2, 1968, spring joint computer conference. ACM, 307--314.

Digital Library

[5]

Andrew Bitar, Jeffrey Cassidy, Natalie Enright Jerger, and Vaughn Betz. 2014. Efficient and programmable Ethernet switching with a NoC-enhanced FPGA. In Proceedings of the tenth ACM/IEEE symposium on Architectures for networking and communications systems. ACM, 89--100.

Digital Library

[6]

Daniel Bundala and Jakub Závodn

[7]

y. 2014. Optimal sorting networks. In International Conference on Language and Automata Theory and Applications. Springer, 236--247.

[8]

Jonathan Chao. 2000. Saturn: a terabit packet switch using dual round robin. IEEE Communications Magazine 38, 12 (2000), 78--84.

Digital Library

[9]

Shang-Tse Chuang, Ashish Goel, Nick McKeown, and Balaji Prabhakar. 1999. Matching output queueing with a combined input/output-queued switch. IEEE Journal on Selected Areas in Communications 17, 6 (1999), 1030--1039.

Digital Library

[10]

Zefu Dai and Jianwen Zhu. 2012. Saturating the transceiver bandwidth: Switch fabric design on FPGAs. In Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays. ACM, 67--76.

Digital Library

[11]

Nadeen Gebara, Jiuxi Meng, Wayne Luk, and Paolo Costa. 2018. Scheduling Algorithms for High Performance Network Switching on FPGAs: A Survey. In 2018 International Conference on Field-Programmable Technology (FPT). IEEE, 166--173.

[12]

Pankaj Gupta and Nick McKeown. 1999. Designing and implementing a fast crossbar scheduler. IEEE micro 19, 1 (1999), 20--28.

[13]

Chunzhi He and Kwan L Yeung. 2011. D-LQF: An efficient distributed scheduling algorithm for input-queued switches. In 2011 IEEE International Conference on Communications (ICC). IEEE, 1--5.

[14]

W Daniel Hillis and Guy L Steele Jr. 1986. Data parallel algorithms. Commun. ACM 29, 12 (1986), 1170--1183.

Digital Library

[15]

Xilinx Inc. 2015--2019. UltraScale+ FPGA Product Tables and Product Selection Guide.

[16]

Xilinx Inc. 2019. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS923).

[17]

Yossi Kanizo, David Hay, and Isaac Keslassy. 2009. The crosspoint-queued switch. In IEEE INFOCOM 2009. IEEE, 729--737.

[18]

John Kim, William J Dally, Brian Towles, and Amit K Gupta. 2005. Microarchitecture of a high-radix router. In ACM SIGARCH Computer Architecture News, Vol. 33. IEEE Computer Society, 420--431.

Digital Library

[19]

Yihan Li, Shivendra Panwar, and H Jonathan Chao. 2001. On the performance of a dual round-robin switch. In Proceedings IEEE INFOCOM 2001. Conference on Computer Communications. Twentieth Annual Joint Conference of the IEEE Computer and Communications Society (Cat. No. 01CH37213), Vol. 3. IEEE, 1688-- 1697.

[20]

Yihan Li, Shivendra Panwar, and H Jonathan Chao. 2002. The dual round robin matching switch with exhaustive service. In Workshop on High Performance Switching and Routing, Merging Optical and IP Technologie. IEEE, 58--63.

[21]

Mario Ruiz, David Sidler, Gustavo Sutter, Gustavo Alonso and Sergio Lopez- Buedo. 2019. Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack. In 2019 30th International Conference on Field Programmable Logic and Applications (FPL). IEEE.

[22]

Nick McKeown. 1999. The iSLIP scheduling algorithm for input-queued switches. IEEE/ACM transactions on networking 2 (1999), 188--201.

Digital Library

[23]

Jiuxi Meng, Nadeen Gebara, Ho-Cheung Ng, Paolo Costa, and Wayne Luk. 2019. Investigating the Feasibility of FPGA-based Network Switches. In 2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP). IEEE.

[24]

Rene Mueller, Jens Teubner, and Gustavo Alonso. 2012. Sorting networks on FPGAs. The VLDB Journal-The International Journal on Very Large Data Bases 21, 1 (2012), 1--23.

Digital Library

[25]

M Hassan Najafi, David J Lilja, Marc D Riedel, and Kia Bazargan. 2018. Low-cost sorting network circuits using unary processing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26, 8 (2018), 1471--1480.

[26]

Philippos Papaphilippou, Chris Brooks, and Wayne Luk. 2018. FLiMS: Fast Lightweight Merge Sorter. In 2018 International Conference on Field-Programmable Technology (FPT). IEEE, 78--85.

[27]

Philippos Papaphilippou andWayne Luk. 2018. Accelerating database systems using FPGAs: A survey. In 2018 28th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 125--130.

[28]

Philippos Papaphilippou, Holger Pirk, and Wayne Luk. 2019. Accelerating the merge phase of sort-merge join. In 2019 29th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 100--105.

Cited By

Luo JYu FLi WXing Q(2024)A Novel Switch Architecture for Multi-Die Optimization with Efficient ConnectionsElectronics10.3390/electronics1316320513:16(3205)Online publication date: 13-Aug-2024
https://doi.org/10.3390/electronics13163205
Heinz CKalkhof TLavan YKoch A(2024)TaPaS Co-AIE: An Open-Source Framework for Streaming-Based Heterogeneous Acceleration Using AMD AI Engines2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)10.1109/IPDPSW63119.2024.00041(155-161)Online publication date: 27-May-2024
https://doi.org/10.1109/IPDPSW63119.2024.00041
Guo LChi YLau JSong LTian XKhatti MQiao WWang JUstun EFang ZZhang ZCong J(2023)TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical DesignACM Transactions on Reconfigurable Technology and Systems10.1145/3609335Online publication date: 18-Sep-2023
https://doi.org/10.1145/3609335
Show More Cited By

Recommendations

Hipernetch: High-Performance FPGA Network Switch
We present Hipernetch, a novel FPGA-based design for performing high-bandwidth network switching. FPGAs have recently become more popular in data centers due to their promising capabilities for a wide range of applications. With the recent surge in ...
Scalable High Performance SDN Switch Architecture on FPGA for Core Networks
FPGA '19: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

Due to the increasing heterogeneity in network user requirements, dynamically varying day to day network traffic patterns and delay in network service deployment, there is a huge demand for scalability and flexibility in modern networking infrastructure,...
Design and implementation of a reconfigurable arbiter
SSIP'07: Proceedings of the 7th WSEAS International Conference on Signal, Speech and Image Processing

The SOC design paradigm relies on well-defined interfaces and reuse of intellectual property (IP). Because more and more IPs are integrated into the design platform, the amount of communication between the IPs is on the increase and becomes the source ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences

FPGA '20: Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

February 2020

346 pages

ISBN:9781450370998

DOI:10.1145/3373087

General Chair:
Stephen Neuendorffer
Xilinx, USA
,
Program Chair:
Lesley Shannon
Simon Fraser University, Canada

Copyright © 2020 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 24 February 2020

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Funding Sources

CDT project
dunnhumby Ltd.

Conference

FPGA '20

Sponsor:

SIGDA

FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

February 23 - 25, 2020

CA, Seaside, USA

Acceptance Rates

Overall Acceptance Rate 125 of 627 submissions, 20%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

13
Total Citations
View Citations
1,184
Total Downloads

Downloads (Last 12 months)153
Downloads (Last 6 weeks)12

Reflects downloads up to 30 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

Luo JYu FLi WXing Q(2024)A Novel Switch Architecture for Multi-Die Optimization with Efficient ConnectionsElectronics10.3390/electronics1316320513:16(3205)Online publication date: 13-Aug-2024
https://doi.org/10.3390/electronics13163205
Heinz CKalkhof TLavan YKoch A(2024)TaPaS Co-AIE: An Open-Source Framework for Streaming-Based Heterogeneous Acceleration Using AMD AI Engines2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)10.1109/IPDPSW63119.2024.00041(155-161)Online publication date: 27-May-2024
https://doi.org/10.1109/IPDPSW63119.2024.00041
Guo LChi YLau JSong LTian XKhatti MQiao WWang JUstun EFang ZZhang ZCong J(2023)TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical DesignACM Transactions on Reconfigurable Technology and Systems10.1145/3609335Online publication date: 18-Sep-2023
https://doi.org/10.1145/3609335
Ueno TSano K(2023)VCSN: Virtual Circuit-Switching Network for Flexible and Simple-to-Operate Communication in HPC FPGA ClusterACM Transactions on Reconfigurable Technology and Systems10.1145/357984816:2(1-32)Online publication date: 13-Jan-2023
https://dl.acm.org/doi/10.1145/3579848
Papaphilippou PSano KAdhi BLuk W(2023)Experimental Survey of FPGA-Based Monolithic Switches and a Novel Queue BalancerIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2023.324458934:5(1621-1634)Online publication date: May-2023
https://doi.org/10.1109/TPDS.2023.3244589
Papaphilippou PMeng JGebara NLuk W(2022)Hipernetch: High-Performance FPGA Network SwitchACM Transactions on Reconfigurable Technology and Systems10.1145/347705415:1(1-31)Online publication date: 31-Mar-2022
https://dl.acm.org/doi/10.1145/3477054
Papaphilippou PLuk WBrooks C(2022)FLiMS: a Fast Lightweight 2-way Merger for SortingIEEE Transactions on Computers10.1109/TC.2022.3146509(1-1)Online publication date: 2022
https://doi.org/10.1109/TC.2022.3146509
Prakash SPatel HKapre N(2022)Managing HBM Bandwidth on Multi-Die FPGAs with FPGA Overlay NoCs2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM53951.2022.9786203(1-9)Online publication date: 15-May-2022
https://doi.org/10.1109/FCCM53951.2022.9786203
Lai YUstun EXiang SFang ZRong HZhang Z(2021)Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future ProspectsACM Transactions on Reconfigurable Technology and Systems10.1145/346966014:4(1-39)Online publication date: 13-Sep-2021
https://dl.acm.org/doi/10.1145/3469660
Chi YGuo LLau JChoi YWang JCong J(2021)Extending High-Level Synthesis for Task-Parallel Programs2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM51124.2021.00032(204-213)Online publication date: May-2021
https://doi.org/10.1109/FCCM51124.2021.00032
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents