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BitSAD v2: Compiler Optimization and Analysis for Bitstream Computing

Published: 18 November 2019 Publication History

Abstract

Computer vision and machine learning algorithms operating under a strict power budget require an alternate computing paradigm. While bitstream computing (BC) satisfies these constraints, creating BC systems is difficult. To address the design challenges, we propose compiler extensions to BitSAD, a DSL for BC. Our work enables bit-level software emulation and automated generation of hierarchical hardware, discusses potential optimizations, and proposes compiler phases to implement those optimizations in a hardware-aware manner. Finally, we introduce population coding, a parallelization scheme for stochastic computing that decreases latency without sacrificing accuracy, and provide theoretical and experimental guarantees on its effectiveness.

Supplementary Material

a43-daruwalla-suppl.pdf (daruwalla.zip)
Supplemental movie, appendix, image and software files for, BitSAD v2: Compiler Optimization and Analysis for Bitstream Computing

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Cited By

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  • (2024)SCGen: A Versatile Generator Framework for Agile Design of Stochastic Circuits2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546649(1-6)Online publication date: 25-Mar-2024
  • (2023)Energy-Efficient Bayesian Inference Using Bitstream ComputingIEEE Computer Architecture Letters10.1109/LCA.2023.323858422:1(37-40)Online publication date: 1-Jan-2023
  • (2023)High-Speed Compilation of Large-Scale Stochastic Circuits2023 IEEE International Conference on Rebooting Computing (ICRC)10.1109/ICRC60800.2023.10386131(1-4)Online publication date: 5-Dec-2023
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Information

Published In

cover image ACM Transactions on Architecture and Code Optimization
ACM Transactions on Architecture and Code Optimization  Volume 16, Issue 4
December 2019
572 pages
ISSN:1544-3566
EISSN:1544-3973
DOI:10.1145/3366460
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 18 November 2019
Accepted: 01 September 2019
Revised: 01 August 2019
Received: 01 June 2019
Published in TACO Volume 16, Issue 4

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Author Tags

  1. Bitstream computing
  2. compiler
  3. pulse density modulation
  4. stochastic computing

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Cited By

View all
  • (2024)SCGen: A Versatile Generator Framework for Agile Design of Stochastic Circuits2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546649(1-6)Online publication date: 25-Mar-2024
  • (2023)Energy-Efficient Bayesian Inference Using Bitstream ComputingIEEE Computer Architecture Letters10.1109/LCA.2023.323858422:1(37-40)Online publication date: 1-Jan-2023
  • (2023)High-Speed Compilation of Large-Scale Stochastic Circuits2023 IEEE International Conference on Rebooting Computing (ICRC)10.1109/ICRC60800.2023.10386131(1-4)Online publication date: 5-Dec-2023
  • (2021)uGEMM: Unary Computing for GEMM ApplicationsIEEE Micro10.1109/MM.2021.306536941:3(50-56)Online publication date: 1-May-2021
  • (2021)A Python-based evaluation framework for stochastic computing circuits on FPGA SoC2021 Ninth International Symposium on Computing and Networking Workshops (CANDARW)10.1109/CANDARW53999.2021.00021(81-86)Online publication date: Nov-2021

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