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Alleviating Irregularity in Graph Analytics Acceleration: a Hardware/Software Co-Design Approach

Authors:

Yuan XieAuthors Info & Claims

MICRO '52: Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture

Pages 615 - 628

https://doi.org/10.1145/3352460.3358318

Published: 12 October 2019 Publication History

Abstract

Graph analytics is an emerging application which extracts insights by processing large volumes of highly connected data, namely graphs. The parallel processing of graphs has been exploited at the algorithm level, which in turn incurs three irregularities onto computing and memory patterns that significantly hinder an efficient architecture design. Certain irregularities can be partially tackled by the prior domain-specific accelerator designs with well-designed scheduling of data access, while others remain unsolved.

Unlike prior efforts, we fully alleviate these irregularities at their origin---the data-dependent program behavior. To achieve this goal, we propose GraphDynS, a hardware/software co-design with decoupled datapath and data-aware dynamic scheduling. Aware of data dependencies extracted from the decoupled datapath, GraphDynS can elaborately schedule the program on-the-fly to maximize parallelism. To extract data dependencies at runtime, we propose a new programming model in synergy with a microarchitecture design that supports datapath decoupling. Through data dependency information, we present several data-aware strategies to dynamically schedule workloads, data accesses, and computations. Overall, GraphDynS achieves 4.4× speedup and 11.6× less energy on average with half the memory bandwidth compared to a state-of-the-art GPGPU-based solution. Compared to a state-of-the-art graph analytics accelerator, GraphDynS also achieves 1.9× speedup and 1.8× less energy on average using the same memory bandwidth.

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Cited By

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Liu JChen SShen L(2025)A comprehensive survey on graph neural network acceleratorsFrontiers of Computer Science: Selected Publications from Chinese Universities10.1007/s11704-023-3307-219:2Online publication date: 1-Feb-2025
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Mao FLiu XZhang YLiu HLiao XJin HZhang WZhou JWu YNie LGuo YJiang ZLiu J(2024)PMGraph: Accelerating Concurrent Graph Queries over Streaming GraphsACM Transactions on Architecture and Code Optimization10.1145/368933721:4(1-25)Online publication date: 20-Nov-2024
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Index Terms

Alleviating Irregularity in Graph Analytics Acceleration: a Hardware/Software Co-Design Approach
1. Hardware
  1. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific integrated circuits

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MICRO '52: Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture

October 2019

1104 pages

ISBN:9781450369381

DOI:10.1145/3352460

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MICRO '52: The 52nd Annual IEEE/ACM International Symposium on Microarchitecture

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