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FEC Killed The Cut-Through Switch

Published: 07 August 2018 Publication History

Abstract

Latency penalty in Ethernet links beyond 10Gb/s is due to forward error correction (FEC) blocks. In the worst case a single-hop penalty approaches the latency of an entire cut-through switch. Latency jitter is also introduced, making latency prediction harder, with large peak to peak variance. These factors stretch the tail of latency distribution in Rack-scale systems and Data Centers, which in turn degrades performance of distributed applications. We analyse the underlying mechanisms, calculate lower bounds and propose a different approach that would reduce the penalty, allow control over latency and feedback for application level optimisation.

Supplementary Material

Original paper (p15-sella_v1.pdf)
Published on August 20, 2018 in the ACM Digital Library. Replaced on August 23, with approval of the program chairs. A figure was omitted in error.

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  • (2024)Switch-Less Dragonfly on Wafers: A Scalable Interconnection Architecture based on Wafer-Scale IntegrationProceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis10.1109/SC41406.2024.00102(1-17)Online publication date: 17-Nov-2024
  • (2023)Masking Corruption Packet Losses in Datacenter Networks with Link-local RetransmissionProceedings of the ACM SIGCOMM 2023 Conference10.1145/3603269.3604853(288-304)Online publication date: 10-Sep-2023
  • (2021)The pos frameworkProceedings of the 17th International Conference on emerging Networking EXperiments and Technologies10.1145/3485983.3494841(259-266)Online publication date: 2-Dec-2021
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Published In

cover image ACM Conferences
NEAT '18: Proceedings of the 2018 Workshop on Networking for Emerging Applications and Technologies
August 2018
63 pages
ISBN:9781450359078
DOI:10.1145/3229574
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 07 August 2018

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  • Research-article
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SIGCOMM '18
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SIGCOMM '18: ACM SIGCOMM 2018 Conference
August 20, 2018
Budapest, Hungary

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Overall Acceptance Rate 8 of 18 submissions, 44%

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Cited By

View all
  • (2024)Switch-Less Dragonfly on Wafers: A Scalable Interconnection Architecture based on Wafer-Scale IntegrationProceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis10.1109/SC41406.2024.00102(1-17)Online publication date: 17-Nov-2024
  • (2023)Masking Corruption Packet Losses in Datacenter Networks with Link-local RetransmissionProceedings of the ACM SIGCOMM 2023 Conference10.1145/3603269.3604853(288-304)Online publication date: 10-Sep-2023
  • (2021)The pos frameworkProceedings of the 17th International Conference on emerging Networking EXperiments and Technologies10.1145/3485983.3494841(259-266)Online publication date: 2-Dec-2021
  • (2019)Reducing Latency in Virtual Machines: Enabling Tactile Internet for Human-Machine Co-WorkingIEEE Journal on Selected Areas in Communications10.1109/JSAC.2019.290678837:5(1098-1116)Online publication date: May-2019

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