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Breaking POps/J Barrier with Analog Multiplier Circuits Based on Nonvolatile Memories

Published: 23 July 2018 Publication History

Abstract

Low-to-medium resolution analog vector-by-matrix multipliers (VMMs) offer a remarkable energy/area efficiency as compared to their digital counterparts. Still, the maximum attainable performance in analog VMMs is often bounded by the overhead of the peripheral circuits. The main contribution of this paper is the design of novel sensing circuitry which improves energy-efficiency and density of analog multipliers. The proposed circuit is based on translinear Gilbert cell, which is topologically combined with a floating nonlinear resistor and a low-gain amplifier. Several compensation techniques are employed to ensure reliability with respect to process, temperature, and supply voltage variations. As a case study, we consider implementation of couple-gate current-mode VMM with embedded split-gate NOR flash memory. Our simulation results show that a 4-bit 100x100 VMM circuit designed in 55 nm CMOS technology achieves the record-breaking performance of 3.63 POps/J.

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Cited By

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  • (2020)Intrinsic Bounds for Computing Precision in Memristor-Based Vector-by-Matrix MultipliersIEEE Transactions on Nanotechnology10.1109/TNANO.2020.299249319(429-435)Online publication date: 2020
  • (2020)Lightweight Integrated Design of PUF and TRNG Security Primitives Based on eFlash Memory in 55-nm CMOSIEEE Transactions on Electron Devices10.1109/TED.2020.297663267:4(1586-1592)Online publication date: Apr-2020
  • (2019)ChipSecureProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3324890(1-6)Online publication date: 2-Jun-2019
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  1. Breaking POps/J Barrier with Analog Multiplier Circuits Based on Nonvolatile Memories

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    cover image ACM Conferences
    ISLPED '18: Proceedings of the International Symposium on Low Power Electronics and Design
    July 2018
    327 pages
    ISBN:9781450357043
    DOI:10.1145/3218603
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 23 July 2018

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    Author Tags

    1. Analog Computing
    2. Artificial Neural Networks
    3. Current Processing
    4. Floating-Gate Memory
    5. Sensing Circuit
    6. Vector-Matrix Multiplier

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    Cited By

    View all
    • (2020)Intrinsic Bounds for Computing Precision in Memristor-Based Vector-by-Matrix MultipliersIEEE Transactions on Nanotechnology10.1109/TNANO.2020.299249319(429-435)Online publication date: 2020
    • (2020)Lightweight Integrated Design of PUF and TRNG Security Primitives Based on eFlash Memory in 55-nm CMOSIEEE Transactions on Electron Devices10.1109/TED.2020.297663267:4(1586-1592)Online publication date: Apr-2020
    • (2019)ChipSecureProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3324890(1-6)Online publication date: 2-Jun-2019
    • (2019)Improving Noise Tolerance of Mixed-Signal Neural Networks2019 International Joint Conference on Neural Networks (IJCNN)10.1109/IJCNN.2019.8851966(1-8)Online publication date: Jul-2019
    • (2018)Mixed-Signal Neuromorphic Inference Accelerators: Recent Results and Future Prospects2018 IEEE International Electron Devices Meeting (IEDM)10.1109/IEDM.2018.8614659(20.4.1-20.4.4)Online publication date: Dec-2018

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