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swSpTRSV: a fast sparse triangular solve with sparse level tile layout on sunway architectures

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Li WuAuthors Info & Claims

ACM SIGPLAN Notices, Volume 53, Issue 1

Pages 338 - 353

https://doi.org/10.1145/3200691.3178513

Published: 10 February 2018 Publication History

Abstract

Sparse triangular solve (SpTRSV) is one of the most important kernels in many real-world applications. Currently, much research on parallel SpTRSV focuses on level-set construction for reducing the number of inter-level synchronizations. However, the out-of-control data reuse and high cost for global memory or shared cache access in inter-level synchronization have been largely neglected in existing work.

In this paper, we propose a novel data layout called Sparse Level Tile to make all data reuse under control, and design a Producer-Consumer pairing method to make any inter-level synchronization only happen in very fast register communication. We implement our data layout and algorithms on an SW26010 many-core processor, which is the main building-block of the current world fastest supercomputer Sunway Taihulight. The experimental results of testing all 2057 square matrices from the Florida Matrix Collection show that our method achieves an average speedup of 6.9 and the best speedup of 38.5 over parallel level-set method. Our method also outperforms the latest methods on a KNC many-core processor in 1856 matrices and the latest methods on a K80 GPU in 1672 matrices, respectively.

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Cited By

Lu ZLiu W(2023)TileSpTRSV: a tiled algorithm for parallel sparse triangular solve on GPUsCCF Transactions on High Performance Computing10.1007/s42514-023-00151-15:2(129-143)Online publication date: 12-Jun-2023
https://doi.org/10.1007/s42514-023-00151-1
Li MLiu YChen BYang HLuan ZQian D(2023)Building a domain-specific compiler for emerging processors with a reusable approachScience China Information Sciences10.1007/s11432-022-3727-667:1Online publication date: 27-Dec-2023
https://doi.org/10.1007/s11432-022-3727-6
Zhang FSu JLiu WHe BWu RDu XWang R(2021)YuenyeungSpTRSV: A Thread-Level and Warp-Level Fusion Synchronization-Free Sparse Triangular SolveIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2021.306663532:9(2321-2337)Online publication date: 1-Sep-2021
https://dl.acm.org/doi/10.1109/TPDS.2021.3066635
Show More Cited By

Index Terms

swSpTRSV: a fast sparse triangular solve with sparse level tile layout on sunway architectures
1. Theory of computation
  1. Design and analysis of algorithms
    1. Parallel algorithms

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Published In

cover image ACM SIGPLAN Notices

ACM SIGPLAN Notices Volume 53, Issue 1

PPoPP '18

January 2018

426 pages

ISSN:0362-1340

EISSN:1558-1160

DOI:10.1145/3200691

Editor:
Matthew Fluet
Rodchester Institude of Technology

Issue’s Table of Contents

PPoPP '18: Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
February 2018
442 pages
ISBN:9781450349826
DOI:10.1145/3178487
General Chair:
Andreas Krall
Vienna University of Technology, Austria
,
Program Chair:
Thomas R. Gross
ETH Zürich, Switzerland

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Published: 10 February 2018

Published in SIGPLAN Volume 53, Issue 1

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National Key R&D Program of China
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Cited By

Lu ZLiu W(2023)TileSpTRSV: a tiled algorithm for parallel sparse triangular solve on GPUsCCF Transactions on High Performance Computing10.1007/s42514-023-00151-15:2(129-143)Online publication date: 12-Jun-2023
https://doi.org/10.1007/s42514-023-00151-1
Li MLiu YChen BYang HLuan ZQian D(2023)Building a domain-specific compiler for emerging processors with a reusable approachScience China Information Sciences10.1007/s11432-022-3727-667:1Online publication date: 27-Dec-2023
https://doi.org/10.1007/s11432-022-3727-6
Zhang FSu JLiu WHe BWu RDu XWang R(2021)YuenyeungSpTRSV: A Thread-Level and Warp-Level Fusion Synchronization-Free Sparse Triangular SolveIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2021.306663532:9(2321-2337)Online publication date: 1-Sep-2021
https://dl.acm.org/doi/10.1109/TPDS.2021.3066635
Xu KDuan XMüller AKobus RSchmidt BLiu W(2021)FMapper: Scalable Read Mapper based on Succinct Hash Index on SunWay TaihuLightJournal of Parallel and Distributed Computing10.1016/j.jpdc.2021.11.004Online publication date: Nov-2021
https://doi.org/10.1016/j.jpdc.2021.11.004
Dufrechou EEzzatti PFreire MQuintana-Ortí E(2021)Machine learning for optimal selection of sparse triangular system solvers on GPUsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2021.07.013158:C(47-55)Online publication date: 1-Dec-2021
https://dl.acm.org/doi/10.1016/j.jpdc.2021.07.013
Dun MLi YSun QYang HLi WLuan ZGan LYang GQian D(2021)Towards efficient canonical polyadic decomposition on sunway many-core processorInformation Sciences10.1016/j.ins.2020.11.013549(221-248)Online publication date: Mar-2021
https://doi.org/10.1016/j.ins.2020.11.013
Yılmaz BSipahioğrlu BAhmad NUnat D(2020)Adaptive Level BinningProceedings of the International Conference on High Performance Computing in Asia-Pacific Region10.1145/3368474.3368486(188-198)Online publication date: 15-Jan-2020
https://dl.acm.org/doi/10.1145/3368474.3368486
Li MLiu YYang HLuan ZGan LYang GQian D(2020)Accelerating Sparse Cholesky Factorization on Sunway Manycore ArchitectureIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2019.295385231:7(1636-1650)Online publication date: 3-Mar-2020
https://dl.acm.org/doi/10.1109/TPDS.2019.2953852
Jin SPei SWang YQi Y(2020)A parallel sparse triangular solve algorithm based on dependency elimination of the solution vectorCluster Computing10.1007/s10586-020-03188-xOnline publication date: 3-Oct-2020
https://doi.org/10.1007/s10586-020-03188-x
Chen BLi MYang HLuan ZGan LYang GQian D(2020)swRodinia: A Benchmark Suite for Exploiting Architecture Properties of Sunway ProcessorBenchmarking, Measuring, and Optimizing10.1007/978-3-030-71058-3_2(22-38)Online publication date: 15-Nov-2020
https://dl.acm.org/doi/10.1007/978-3-030-71058-3_2
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