research-article

MirrorCache: An Energy-Efficient Relaxed Retention L1 STTRAM Cache

Authors:

Kyle Kuan,

Tosiron AdegbijaAuthors Info & Claims

GLSVLSI '19: Proceedings of the 2019 Great Lakes Symposium on VLSI

Pages 299 - 302

https://doi.org/10.1145/3299874.3318022

Published: 13 May 2019 Publication History

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Abstract

Spin-Transfer Torque RAM (STTRAM) is a promising alternative to SRAMs in on-chip caches, due to several advantages, including non-volatility, low leakage, high integration density, and CMOS compatibility. However, STTRAMs' wide adoption in resource-constrained systems is impeded, in part, by high write energy and latency. A popular approach to mitigating these overheads involves relaxing the STTRAM's retention time, in order to reduce the write latency and energy. However, this approach usually requires a dynamic refresh scheme to maintain cache blocks' data integrity beyond the retention time, and typically requires an external refresh buffer. In this paper, we propose mirrorCache---an energy-efficient, buffer-free refresh scheme. MirrorCache leverages the STTRAM cell's compact feature size, and uses an auxiliary segment with the same size as the logical cache size to handle the refresh operations without the overheads of an external refresh buffer. Our experiments show that, compared to prior work, mirrorCache can reduce the average cache energy by at least 39.7% for a variety of systems.

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Karunakar SAtkade MPoptani AKalayappan RChandran S(2024)CASH: Criticality-Aware Split Hybrid L1 Data CacheProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3658716(50-56)Online publication date: 12-Jun-2024
https://dl.acm.org/doi/10.1145/3649476.3658716
Cai TGao PNiu DMa YLei TDai J(2023)NEHASH: high-concurrency extendible hashing for non-volatile memoryNEHASH:面向非易失性内存的高并发可扩展哈希Frontiers of Information Technology & Electronic Engineering10.1631/FITEE.220046224:5(703-715)Online publication date: 2-Jun-2023
https://doi.org/10.1631/FITEE.2200462
Manohar SKapoor H(2023)CAPMIG: Coherence-Aware Block Placement and Migration in Multiretention STT-RAM CachesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.317524242:2(411-422)Online publication date: Feb-2023
https://doi.org/10.1109/TCAD.2022.3175242
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Index Terms

MirrorCache: An Energy-Efficient Relaxed Retention L1 STTRAM Cache
1. Computer systems organization
  1. Dependable and fault-tolerant systems and networks
    1. Processors and memory architectures

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Published In

GLSVLSI '19: Proceedings of the 2019 Great Lakes Symposium on VLSI

May 2019

562 pages

ISBN:9781450362528

DOI:10.1145/3299874

General Chairs:
Houman Homayoun
George Mason University, USA
,
Baris Taskin
Drexel University, USA
,
Program Chairs:
Tinoosh Mohsenin
UMBC, USA
,
Weisheng Zhao
Beihang University, China

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

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Published: 13 May 2019

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GLSVLSI '19: Great Lakes Symposium on VLSI 2019

May 9 - 11, 2019

VA, Tysons Corner, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

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Karunakar SAtkade MPoptani AKalayappan RChandran S(2024)CASH: Criticality-Aware Split Hybrid L1 Data CacheProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3658716(50-56)Online publication date: 12-Jun-2024
https://dl.acm.org/doi/10.1145/3649476.3658716
Cai TGao PNiu DMa YLei TDai J(2023)NEHASH: high-concurrency extendible hashing for non-volatile memoryNEHASH:面向非易失性内存的高并发可扩展哈希Frontiers of Information Technology & Electronic Engineering10.1631/FITEE.220046224:5(703-715)Online publication date: 2-Jun-2023
https://doi.org/10.1631/FITEE.2200462
Manohar SKapoor H(2023)CAPMIG: Coherence-Aware Block Placement and Migration in Multiretention STT-RAM CachesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.317524242:2(411-422)Online publication date: Feb-2023
https://doi.org/10.1109/TCAD.2022.3175242
Agarwal SChakraborty SSjälander M(2023)Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR)2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247878(1-6)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247878
Cai TMa YLiu PNiu DLi L(2022)A New NVM Device Driver for IoT Time Series DatabaseMicromachines10.3390/mi1303038513:3(385)Online publication date: 27-Feb-2022
https://doi.org/10.3390/mi13030385
Baranwal MChugh UDalal SAgarwal SKapoor H(2021)DAMUS: Dynamic Allocation based on Write Frequency in MUlti-Retention STT-RAM based Last Level Caches2021 22nd International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED51717.2021.9424250(469-475)Online publication date: 7-Apr-2021
https://doi.org/10.1109/ISQED51717.2021.9424250
Agarwal SChakraborty S(2021)ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache2021 IEEE 32nd International Conference on Application-specific Systems, Architectures and Processors (ASAP)10.1109/ASAP52443.2021.00032(171-174)Online publication date: Jul-2021
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Suman SKapoor H(2020)Reinforcement Learning Based Refresh Optimized Volatile STT-RAM Cache2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI49217.2020.00048(222-227)Online publication date: Jul-2020
https://doi.org/10.1109/ISVLSI49217.2020.00048

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