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Power scalable processing using distributed arithmetic

Authors:

Rajeevan Amirtharajah,

Thucydides Xanthopoulos,

Anantha ChandrakasanAuthors Info & Claims

ISLPED '99: Proceedings of the 1999 international symposium on Low power electronics and design

Pages 170 - 175

https://doi.org/10.1145/313817.313911

Published: 17 August 1999 Publication History

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Cited By

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Riemens DGaydadjiev GZeeuw CStrydis C(2014)Towards scalable arithmetic units with graceful degradationACM Transactions on Embedded Computing Systems10.1145/249936713:4(1-26)Online publication date: 10-Mar-2014
https://dl.acm.org/doi/10.1145/2499367
Wenck JCollier JSiebert JAmirtharajah R(2008)Scaling self-timed systems powered by mechanical vibration energy harvestingACM Journal on Emerging Technologies in Computing Systems10.1145/1773814.17738166:2(1-24)Online publication date: 18-Jun-2008
https://dl.acm.org/doi/10.1145/1773814.1773816
Zhong GXu FWillson A(2006)A Power-Scalable Reconfigurable FFT/IFFT IC Based on a Multi-Processor RingIEEE Journal of Solid-State Circuits10.1109/JSSC.2005.86234441:2(483-495)Online publication date: Feb-2006
https://doi.org/10.1109/JSSC.2005.862344
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Index Terms

Power scalable processing using distributed arithmetic
1. Applied computing
  1. Physical sciences and engineering
    1. Electronics
2. Hardware
  1. Communication hardware, interfaces and storage
    1. Signal processing systems
  2. Very large scale integration design

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Information & Contributors

Information

Published In

ISLPED '99: Proceedings of the 1999 international symposium on Low power electronics and design

August 1999

295 pages

ISBN:158113133X

DOI:10.1145/313817

Chairmen:
Farid N. Najim
Univ. of Illinois at Urbana-Champaign
,
Jason Cong
UCLA
,
David Blaauw
Motorola

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 17 August 1999

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ISLPED99

Sponsor:

SIGDA
IEEE-CAS

ISLPED99: International Symposium on Low Power Electronics and Design

August 16 - 17, 1999

California, San Diego, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

View all

Riemens DGaydadjiev GZeeuw CStrydis C(2014)Towards scalable arithmetic units with graceful degradationACM Transactions on Embedded Computing Systems10.1145/249936713:4(1-26)Online publication date: 10-Mar-2014
https://dl.acm.org/doi/10.1145/2499367
Wenck JCollier JSiebert JAmirtharajah R(2008)Scaling self-timed systems powered by mechanical vibration energy harvestingACM Journal on Emerging Technologies in Computing Systems10.1145/1773814.17738166:2(1-24)Online publication date: 18-Jun-2008
https://dl.acm.org/doi/10.1145/1773814.1773816
Zhong GXu FWillson A(2006)A Power-Scalable Reconfigurable FFT/IFFT IC Based on a Multi-Processor RingIEEE Journal of Solid-State Circuits10.1109/JSSC.2005.86234441:2(483-495)Online publication date: Feb-2006
https://doi.org/10.1109/JSSC.2005.862344
Chen KGuo JWang JYeh CChen J(2005)An energy-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transformsIEEE Transactions on Circuits and Systems for Video Technology10.1109/TCSVT.2005.84644115:5(704-715)Online publication date: 1-May-2005
https://dl.acm.org/doi/10.1109/TCSVT.2005.846441
Abid ZWei Wang Yaobin Chen (2005)Low-power FPGA implementation for DA-based video processingProceedings of 2005 IEEE International Workshop on VLSI Design and Video Technology, 2005.10.1109/IWVDVT.2005.1504625(361-364)Online publication date: 2005
https://doi.org/10.1109/IWVDVT.2005.1504625
Shim BSridhara SShanbhag N(2004)Reliable low-power digital signal processing via reduced precision redundancyIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2004.82620112:5(497-510)Online publication date: 1-May-2004
https://dl.acm.org/doi/10.1109/TVLSI.2004.826201
Rei-Chin Ju Jia-Wei Chen Jiun-In Guo Tien-Fu Chen (2004)A parameterized power-aware IP core generator for the 2-D 8×8 DCT/IDCT2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)10.1109/ISCAS.2004.1329385(II-769-72)Online publication date: 2004
https://doi.org/10.1109/ISCAS.2004.1329385
Chih-Da Chien Chien-Chang Lin Jiun-In Guo Tien-Fu Chen (2004)A power-aware IP core generator for the one-dimensional discrete Fourier transform2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)10.1109/ISCAS.2004.1328827(III-637-40)Online publication date: 2004
https://doi.org/10.1109/ISCAS.2004.1328827
Sridhara SShanbhag N(2001)Low-power FFT via reduced precision redundancy2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)10.1109/SIPS.2001.957337(117-124)Online publication date: 2001
https://doi.org/10.1109/SIPS.2001.957337
Radecka KZilic Z(2001)Arithmetic transforms for verifying compositions of sequential datapathsProceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 200110.1109/ICCD.2001.955050(348-353)Online publication date: 2001
https://doi.org/10.1109/ICCD.2001.955050
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