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Single-phase source-coupled adiabatic logic

Authors:

Suhwan Kim,

Marios C. PapaefthymiouAuthors Info & Claims

ISLPED '99: Proceedings of the 1999 international symposium on Low power electronics and design

Pages 97 - 99

https://doi.org/10.1145/313817.313876

Published: 17 August 1999 Publication History

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Cited By

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Sanadhya MSharma D(2023)Study of Adiabatic Logic-Based Combinational and Sequential Circuits for Low-Power ApplicationsLow Power Architectures for IoT Applications10.1007/978-981-99-0639-0_3(47-84)Online publication date: 5-Apr-2023
https://doi.org/10.1007/978-981-99-0639-0_3
Sharma SDevasia RSharma G(2020)A novel low power and highly efficient inverter designInternational Journal of Information Technology10.1007/s41870-020-00512-xOnline publication date: 5-Sep-2020
https://doi.org/10.1007/s41870-020-00512-x
Dutta KChattopadhyay SBiswas VGhatak S(2019)Design of Power Efficient Vedic Multiplier using Adiabatic Logic2019 International Conference on Electrical, Electronics and Computer Engineering (UPCON)10.1109/UPCON47278.2019.8980057(1-6)Online publication date: Nov-2019
https://doi.org/10.1109/UPCON47278.2019.8980057
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Index Terms

Single-phase source-coupled adiabatic logic
1. Applied computing
  1. Physical sciences and engineering
    1. Electronics
2. Hardware
  1. Hardware validation
    1. Functional verification
      1. Simulation and emulation
  2. Integrated circuits
    1. Logic circuits
    2. Semiconductor memory

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Information & Contributors

Information

Published In

ISLPED '99: Proceedings of the 1999 international symposium on Low power electronics and design

August 1999

295 pages

ISBN:158113133X

DOI:10.1145/313817

Chairmen:
Farid N. Najim
Univ. of Illinois at Urbana-Champaign
,
Jason Cong
UCLA
,
David Blaauw
Motorola

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 17 August 1999

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Sponsor:

SIGDA
IEEE-CAS

ISLPED99: International Symposium on Low Power Electronics and Design

August 16 - 17, 1999

California, San Diego, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

View all

Sanadhya MSharma D(2023)Study of Adiabatic Logic-Based Combinational and Sequential Circuits for Low-Power ApplicationsLow Power Architectures for IoT Applications10.1007/978-981-99-0639-0_3(47-84)Online publication date: 5-Apr-2023
https://doi.org/10.1007/978-981-99-0639-0_3
Sharma SDevasia RSharma G(2020)A novel low power and highly efficient inverter designInternational Journal of Information Technology10.1007/s41870-020-00512-xOnline publication date: 5-Sep-2020
https://doi.org/10.1007/s41870-020-00512-x
Dutta KChattopadhyay SBiswas VGhatak S(2019)Design of Power Efficient Vedic Multiplier using Adiabatic Logic2019 International Conference on Electrical, Electronics and Computer Engineering (UPCON)10.1109/UPCON47278.2019.8980057(1-6)Online publication date: Nov-2019
https://doi.org/10.1109/UPCON47278.2019.8980057
Sarma TParikh C(2019)Effect of Leakage Currents in Adiabatic Logic Circuits at Lower Technology Nodes2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India)10.1109/MOS-AK.2019.8902360(79-81)Online publication date: Feb-2019
https://doi.org/10.1109/MOS-AK.2019.8902360
Jain SPandey N(2019)Single Clock Diode Based Adiabatic Logic Family at Sub-90nm RegimeAdvances in Electronics Engineering10.1007/978-981-15-1289-6_23(245-259)Online publication date: 17-Dec-2019
https://doi.org/10.1007/978-981-15-1289-6_23
Jain SPandey NGupta K(2018)Complete Charge Recovery Diode Free Adiabatic Logic2018 5th International Conference on Signal Processing and Integrated Networks (SPIN)10.1109/SPIN.2018.8474225(656-660)Online publication date: Feb-2018
https://doi.org/10.1109/SPIN.2018.8474225
Kalyani PKumar PSekhar P(2017)Design of subthreshold adiabatic logic based combinational and sequential circuits2017 International Conference on Emerging Trends & Innovation in ICT (ICEI)10.1109/ETIICT.2017.7977002(9-14)Online publication date: Feb-2017
https://doi.org/10.1109/ETIICT.2017.7977002
Chanda MSinha DBasak JGanguli TSarkar C(2016)Design and analysis of adiabatic complex sequential logic circuits in sub-threshold regime for ultra-low power application2016 International Conference on Communication and Signal Processing (ICCSP)10.1109/ICCSP.2016.7754506(1921-1926)Online publication date: Apr-2016
https://doi.org/10.1109/ICCSP.2016.7754506
Sathe VArekapudi SIshii AOuyang CPapaefthymiou MNaffziger S(2013)Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 MicroprocessorIEEE Journal of Solid-State Circuits10.1109/JSSC.2012.221806848:1(140-149)Online publication date: Jan-2013
https://doi.org/10.1109/JSSC.2012.2218068
Kao JMa WSathe VPapaefthymiou M(2012)Energy-efficient low-latency 600 MHz FIR with high-overdrive charge-recovery logicIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.214034620:6(977-988)Online publication date: 1-Jun-2012
https://dl.acm.org/doi/10.1109/TVLSI.2011.2140346
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