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View all- Plassan GMorin-Allory KBorrione D(2019)Mining Missing Assumptions from Counter-ExamplesACM Transactions on Embedded Computing Systems10.1145/328875918:1(1-25)Online publication date: 25-Jan-2019
During the formal functional verification of Register-Transfer Level designs, a false failure is often observed. Most of the time, this failure is caused by an underconstrained model. The analysis of the root cause for the verification error and the ...
We present a framework for the formal verification of abstract state machine (ASM) designs using the multiway decision graphs (MDG) tool. ASM is a state based language for describing transition systems. MDG provides symbolic representation of transition ...
Embedded electronics today are becoming increasingly complex, which makes their design and analysis more and more difficult. In this paper, we focus on the formal verification of embedded system designs at multiple levels of abstraction, enabled by the ...
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