[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ skip to main content
10.1145/3194554.3194591acmconferencesArticle/Chapter ViewAbstractPublication PagesglsvlsiConference Proceedingsconference-collections
research-article

SARO: A State-Aware Reliability Optimization Technique for High Density NAND Flash Memory

Published: 30 May 2018 Publication History

Abstract

Recent advances in flash technologies, such as scaling and multi-leveling schemes, have been successful to make flash denser and secure more storage spaces per die. Unfortunately, these technology advances significantly degrade flash's reliability due to a smaller cell geometry and a finer-grained cell state control. In this paper, we propose a state-aware reliability optimization technique SARO), new flash optimization that improves the flash reliability under diverse scaling and multi-leveling schemes. To this end, we first reveal that reliability-related flash errors are highly skewed among flash cell states, which was not captured by prior studies. The proposed SARO exploits then the different per-state error behavior in flash cell states by selecting the most error-prone flash states (for each error type) and by forming narrow threshold voltage distributions(for the selected states only). Furthermore, SARO is applied only when the program time gets shorter because of flash cell aging, thereby keeping the program latency unchanged. Our experimental results with real MLC and TLC flash devices show that SARO can reduce a significant number of flash bit errors, which can in turn reduce the read latency by 40%, on average.

References

[1]
Y. Park et al. 2014. Scaling and Reliability of NAND Flash Devices. In Proc. IEEE Int. Reliability Physics Symposium.
[2]
Y. Woo et al. 2013. Diversifying Wear Index for MLC NAND Flash Memory to Extend the Lifetime of SSDs Proc. Int. Conf. on Embedded Software.
[3]
R. Micheloni et al. 2010. Inside NAND Flash Memories. Springer.
[4]
N. Mielke et al. 2017. Reliability of Solid-State Drives Based on NAND Flash Memory Proc. IEEE, Vol. Vol. 105(9). 1725--1750.
[5]
Y. Cai et al. 2015. Data retention in MLC NAND flash memory: Characterization, optimization, and recovery IEEE Int. Symposium on High Performance Computer Architecture.
[6]
K. Suh et al. 1995. A 3.3V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme IEEE Tran. on Consumer Electronics, Vol. Vol. 30(11). 1149--1156.
[7]
Y. Pan et al. 2011. Exploiting Memory Device Wear-Out Dynamics to Improve NAND Flash Memory System Performance Proc. USENIX Conf. on File and Storage Technologies.
[8]
S. Park et al. 2012. Adaptive Program Verify Scheme for Improving NAND Flash Memory Performance and Lifespan IEEE Asian Solid-State Circuits Conf.
[9]
J. Jeong et al. 2014. Lifetime Improvement of NAND Flash-based Storage Systems Using Dynamic Program and Erase Scaling Proc. USENIX Conf. on File and Storage Technologies.

Cited By

View all
  • (2024)HAIPO: Hybrid AI Algorithm-Based Post-Fabrication Optimization for Modern 3D NAND Flash MemoryProcesses10.3390/pr1212276012:12(2760)Online publication date: 4-Dec-2024
  • (2023)LazyRS: Improving the Performance and Reliability of High-Capacity TLC/QLC Flash-Based Storage Systems Using Lazy ReprogrammingElectronics10.3390/electronics1204084312:4(843)Online publication date: 7-Feb-2023
  • (2023)CDS: Coupled Data Storage to Enhance Read Performance of 3D TLC NAND Flash MemoryIEEE Transactions on Computers10.1109/TC.2023.333847473:3(694-707)Online publication date: 7-Dec-2023
  • Show More Cited By

Recommendations

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences
GLSVLSI '18: Proceedings of the 2018 Great Lakes Symposium on VLSI
May 2018
533 pages
ISBN:9781450357241
DOI:10.1145/3194554
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 30 May 2018

Permissions

Request permissions for this article.

Check for updates

Author Tags

  1. ispp management
  2. nand flash memory
  3. nand flash performance
  4. nand flash reliability optimization
  5. nand flash retention

Qualifiers

  • Research-article

Funding Sources

  • Samsung Research Funding & Incubation Center of Samsung Electronics

Conference

GLSVLSI '18
Sponsor:
GLSVLSI '18: Great Lakes Symposium on VLSI 2018
May 23 - 25, 2018
IL, Chicago, USA

Acceptance Rates

GLSVLSI '18 Paper Acceptance Rate 48 of 197 submissions, 24%;
Overall Acceptance Rate 312 of 1,156 submissions, 27%

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)30
  • Downloads (Last 6 weeks)6
Reflects downloads up to 04 Jan 2025

Other Metrics

Citations

Cited By

View all
  • (2024)HAIPO: Hybrid AI Algorithm-Based Post-Fabrication Optimization for Modern 3D NAND Flash MemoryProcesses10.3390/pr1212276012:12(2760)Online publication date: 4-Dec-2024
  • (2023)LazyRS: Improving the Performance and Reliability of High-Capacity TLC/QLC Flash-Based Storage Systems Using Lazy ReprogrammingElectronics10.3390/electronics1204084312:4(843)Online publication date: 7-Feb-2023
  • (2023)CDS: Coupled Data Storage to Enhance Read Performance of 3D TLC NAND Flash MemoryIEEE Transactions on Computers10.1109/TC.2023.333847473:3(694-707)Online publication date: 7-Dec-2023
  • (2022)Flash-Cosmos: In-Flash Bulk Bitwise Operations Using Inherent Computation Capability of NAND Flash MemoryProceedings of the 55th Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO56248.2022.00069(937-955)Online publication date: 1-Oct-2022
  • (2021)Data Pattern Aware Reliability Enhancement Scheme for 3D Solid-State DrivesACM Transactions on Embedded Computing Systems10.1145/347700020:5s(1-20)Online publication date: 17-Sep-2021
  • (2021)RealWearACM SIGMETRICS Performance Evaluation Review10.1145/3453953.345398048:3(120-121)Online publication date: 5-Mar-2021
  • (2021)Reparo: A Fast RAID Recovery Scheme for Ultra-large SSDsACM Transactions on Storage10.1145/345097717:3(1-24)Online publication date: 16-Aug-2021
  • (2021)RealWear: Improving performance and lifetime of SSDs using a NAND aging markerPerformance Evaluation10.1016/j.peva.2020.102153145(102153)Online publication date: Jan-2021

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media