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POSTER: HythTM: Extending the Applicability of Intel TSX Hardware Transactional Support

Published: 26 January 2017 Publication History

Abstract

In this work, we introduce and experimentally evaluate a new hybrid software-hardware Transactional Memory prototype based on Intel's Haswell TSX architecture. Our prototype extends the applicability of the existing hardware support for TM by interposing a hybrid fall-back layer before the sequential, big-lock fall-back path, used by standard TSX-supported solutions in order to guarantee progress. In our experimental evaluation we use SynQuake, a realistic game benchmark modeled after Quake. Our results show that our hybrid transactional system,which we call HythTM, is able to reduce the number of transactions that go to the sequential software layer, hence avoiding hardware transaction aborts and loss of parallelism. HythTM optimizes application throughput and scalability up to 5.05x, when compared to the hardware TM with sequential fall-back path.

References

[1]
M. Burcea. Using Variable Conflict Granularity to Improve the Performance of Transactional Memory Support for Games. PhD thesis, University of Toronto, 2015.
[2]
M. Dai Wang, M. Burcea, L. Li, S. Sharifymoghaddam, G. Steffan, and C. Amza. Exploring the performance and programmability design space of hardware transactional memory. In ACM SIGPLAN Workshop on Transactional Computing (TRANSACT), 2014.
[3]
D. Lupei, B. Simion, D. Pinto, M. Misler, M. Burcea, W. Krick, and C. Amza. Transactional memory support for scalable and transparent parallelization of multiplayer games. In Proceedings of the 5th European Conference on Computer Systems, EuroSys '10, pages 41--54, 2010.

Cited By

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  • (2017)Providing QoS in contention management for software transactional memory2017 13th International Computer Engineering Conference (ICENCO)10.1109/ICENCO.2017.8289793(231-236)Online publication date: Dec-2017

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  1. POSTER: HythTM: Extending the Applicability of Intel TSX Hardware Transactional Support

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    cover image ACM Conferences
    PPoPP '17: Proceedings of the 22nd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
    January 2017
    476 pages
    ISBN:9781450344937
    DOI:10.1145/3018743
    Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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    New York, NY, United States

    Publication History

    Published: 26 January 2017

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    Author Tags

    1. cache-coherence
    2. commutativity
    3. shared memory parallel programming

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    • (2017)Providing QoS in contention management for software transactional memory2017 13th International Computer Engineering Conference (ICENCO)10.1109/ICENCO.2017.8289793(231-236)Online publication date: Dec-2017

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