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Adapting cache line size to application behavior

Authors:

Alexander V. Veidenbaum,

Weiyu Tang,

Rajesh Gupta,

Alexandru Nicolau,

Xiaomei JiAuthors Info & Claims

ICS '99: Proceedings of the 13th international conference on Supercomputing

Pages 145 - 154

https://doi.org/10.1145/305138.305188

Published: 01 May 1999 Publication History

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Cited By

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Gajaria DAdegbija T(2022)Evaluating the performance and energy of STT-RAM caches for real-world wearable workloadsFuture Generation Computer Systems10.1016/j.future.2022.05.023136(231-240)Online publication date: Nov-2022
https://doi.org/10.1016/j.future.2022.05.023
Bedoukian PAdit NPeguero ESampson A(2021)Software-Defined Vector Processing on Manycore FabricsMICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3466752.3480099(392-406)Online publication date: 18-Oct-2021
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Zhang CZeng YGuo X(2020)Scrabble: A Fine-Grained Cache with Adaptive Merged BlockIEEE Transactions on Computers10.1109/TC.2019.293980969:1(112-125)Online publication date: 1-Jan-2020
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Published In

ICS '99: Proceedings of the 13th international conference on Supercomputing

June 1999

509 pages

ISBN:158113164X

DOI:10.1145/305138

Chairmen:
Theodore Papatheodorou
Univ. of Patras, Patras, Greece
,
Mateo Valero
Univ. Politècnica de Catalunya, Barcelona, Spain
,
Constantine D. Polychronopoulos
Univ. of Illinois
,
Yoichi Muraoka
Waseda Univ.
,
Jesus Labarta
Univ. Politècnica de Catalunya, Barcelona, Spain

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 1999

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ICS99: The 13th ACM International Conference on Supercomputing

June 20 - 25, 1999

Rhodes, Greece

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ICS '99 Paper Acceptance Rate 57 of 180 submissions, 32%;

Overall Acceptance Rate 629 of 2,180 submissions, 29%

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Gajaria DAdegbija T(2022)Evaluating the performance and energy of STT-RAM caches for real-world wearable workloadsFuture Generation Computer Systems10.1016/j.future.2022.05.023136(231-240)Online publication date: Nov-2022
https://doi.org/10.1016/j.future.2022.05.023
Bedoukian PAdit NPeguero ESampson A(2021)Software-Defined Vector Processing on Manycore FabricsMICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3466752.3480099(392-406)Online publication date: 18-Oct-2021
https://dl.acm.org/doi/10.1145/3466752.3480099
Zhang CZeng YGuo X(2020)Scrabble: A Fine-Grained Cache with Adaptive Merged BlockIEEE Transactions on Computers10.1109/TC.2019.293980969:1(112-125)Online publication date: 1-Jan-2020
https://doi.org/10.1109/TC.2019.2939809
Li BWei JSun JAnnavaram MKim N(2019)An Efficient GPU Cache Architecture for Applications with Irregular Memory Access PatternsACM Transactions on Architecture and Code Optimization10.1145/332212716:3(1-24)Online publication date: 17-Jun-2019
https://dl.acm.org/doi/10.1145/3322127
Addisie AKassa HMatthews OBertacco V(2018)Heterogeneous Memory Subsystem for Natural Graph Analytics2018 IEEE International Symposium on Workload Characterization (IISWC)10.1109/IISWC.2018.8573480(134-145)Online publication date: Sep-2018
https://doi.org/10.1109/IISWC.2018.8573480
Guo HHuang LLu YMa SWang Z(2018)DyCache: Dynamic Multi-Grain Cache Management for Irregular Memory Accesses on GPUIEEE Access10.1109/ACCESS.2018.28181936(38881-38891)Online publication date: 2018
https://doi.org/10.1109/ACCESS.2018.2818193
Unlu EMoy C(2017)Bimodal packet aware scheduling for an OFDMA based on-chip RF interconnectJournal of Parallel and Distributed Computing10.1016/j.jpdc.2017.05.002109:C(15-28)Online publication date: 1-Nov-2017
https://dl.acm.org/doi/10.1016/j.jpdc.2017.05.002
Li LHayes ASong SZhang E(2016)Tag-Split Cache for Efficient GPGPU Cache UtilizationProceedings of the 2016 International Conference on Supercomputing10.1145/2925426.2926253(1-12)Online publication date: 1-Jun-2016
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Siddique NGrubel PBadawy ACook J(2016)Cache Utilization as a Locality Metric - A Case Study on the Mantevo Suite2016 International Conference on Computational Science and Computational Intelligence (CSCI)10.1109/CSCI.2016.0110(549-554)Online publication date: Dec-2016
https://doi.org/10.1109/CSCI.2016.0110
Wingbermuehle JCytron RChamberlain RConstantinides GChen D(2015)Superoptimized Memory Subsystems for Streaming ApplicationsProceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2684746.2689069(126-135)Online publication date: 22-Feb-2015
https://dl.acm.org/doi/10.1145/2684746.2689069
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Heterogeneous way-size cache

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