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DReAM: An Approach to Estimate per-Task DRAM Energy in Multicore Systems

Authors:

Francisco J. Cazorla,

Mateo ValeroAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 22, Issue 1

Article No.: 16, Pages 1 - 26

https://doi.org/10.1145/2939370

Published: 23 November 2016 Publication History

Abstract

Accurate per-task energy estimation in multicore systems would allow performing per-task energy-aware task scheduling and energy-aware billing in data centers, among other applications. Per-task energy estimation is challenged by the interaction between tasks in shared resources, which impacts tasks’ energy consumption in uncontrolled ways. Some accurate mechanisms have been devised recently to estimate per-task energy consumed on-chip in multicores, but there is a lack of such mechanisms for DRAM memories. This article makes the case for accurate per-task DRAM energy metering in multicores, which opens new paths to energy/performance optimizations. In particular, the contributions of this article are (i) an ideal per-task energy metering model for DRAM memories; (ii) DReAM, an accurate yet low cost implementation of the ideal model (less than 5% accuracy error when 16 tasks share memory); and (iii) a comparison with standard methods (even distribution and access-count based) proving that DReAM is much more accurate than these other methods.

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Alawneh TSharadqh AAl Sharah AAwada EAlkasassbeh JAl-Rawashdeh AAl-Qaisi A(2024)A Highly Parallel DRAM Architecture to Mitigate Large Access Latency and Improve Energy Efficiency of Modern DRAM SystemsIEEE Access10.1109/ACCESS.2024.351217612(182998-183023)Online publication date: 2024
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Alawneh TJarajreh MAlkasassbeh JSharadqh A(2023)High-Performance and Power-Saving Mechanism for Page Activations Based on Full Independent DRAM Sub-Arrays in Multi-Core SystemsIEEE Access10.1109/ACCESS.2023.329984811(79801-79822)Online publication date: 2023
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DReAM: An Approach to Estimate per-Task DRAM Energy in Multicore Systems

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 22, Issue 1

January 2017

463 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/2948199

Editor:
Naehyuck Chang
Korea Advanced Institute of Science and Technology, Korea

Issue’s Table of Contents

Copyright © 2016 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 23 November 2016

Accepted: 01 May 2016

Revised: 01 May 2016

Received: 01 January 2016

Published in TODAES Volume 22, Issue 1

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Spanish Ministry of Science and Innovation
Chinese Scholarship Council
HiPEAC Network of Excellence
Ministry of Economy and Competitiveness under Ramon y Cajal postdoctoral
IBM and BSC
European Research Council under the European Union's 7th FP ERC

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Cited By

Alawneh TSharadqh AAl Sharah AAwada EAlkasassbeh JAl-Rawashdeh AAl-Qaisi A(2024)A Highly Parallel DRAM Architecture to Mitigate Large Access Latency and Improve Energy Efficiency of Modern DRAM SystemsIEEE Access10.1109/ACCESS.2024.351217612(182998-183023)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3512176
Autsadee YJeevan JMohd Salleh NOthman MIamraksa P(2024)The emergence of maritime logistics database centre (MLDC): A bibliometrics analysisJournal of International Maritime Safety, Environmental Affairs, and Shipping10.1080/25725084.2024.24251528:4Online publication date: 9-Nov-2024
https://doi.org/10.1080/25725084.2024.2425152
Alawneh TJarajreh MAlkasassbeh JSharadqh A(2023)High-Performance and Power-Saving Mechanism for Page Activations Based on Full Independent DRAM Sub-Arrays in Multi-Core SystemsIEEE Access10.1109/ACCESS.2023.329984811(79801-79822)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3299848
Liu QMoreto MAbella JCazorla FValero M(2017)SEDEA: A Sensible Approach to Account DRAM Energy in Multicore Systems2017 29th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)10.1109/SBAC-PAD.2017.17(73-80)Online publication date: Oct-2017
https://doi.org/10.1109/SBAC-PAD.2017.17

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