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Techniques for modulating error resilience in emerging multi-value technologies

Published: 16 May 2016 Publication History

Abstract

There exist extensive ongoing research efforts on emerging atomic scale technologies that have the potential to become an alternative to today's CMOS technologies. A common feature among the investigated technologies is that of multi-value devices, in particular, the possibility of implementing quaternary logic and memory. However, multi-value devices tend to be more sensitive to interferences and, thus, have reduced error resilience. We present an architecture based on multi-value devices where we can trade energy efficiency against error resilience. Important data are encoded in a more robust binary format while error tolerant data is encoded in a quaternary format. We show for eight benchmarks an average energy reduction of 14%, 20%, and 32% for the register file, level-one data cache, and main memory, respectively, and for three integer benchmarks, an energy reduction for arithmetic operations of up to 28%. We also show that for a quaternary technology to be viable a raw bit error rate of one error in 100 million or better is required.

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Cited By

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  • (2019)Partial-Gated Memristor Crossbar for Fast and Power-Efficient Defect-Tolerant TrainingMicromachines10.3390/mi1004024510:4(245)Online publication date: 13-Apr-2019

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Published In

cover image ACM Conferences
CF '16: Proceedings of the ACM International Conference on Computing Frontiers
May 2016
487 pages
ISBN:9781450341288
DOI:10.1145/2903150
  • General Chairs:
  • Gianluca Palermo,
  • John Feo,
  • Program Chairs:
  • Antonino Tumeo,
  • Hubertus Franke
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Publication History

Published: 16 May 2016

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Author Tags

  1. ALU
  2. approximate computing
  3. cache
  4. emerging technologies
  5. energy efficiency
  6. quaternary logic

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CF'16
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CF'16: Computing Frontiers Conference
May 16 - 19, 2016
Como, Italy

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CF '16 Paper Acceptance Rate 30 of 94 submissions, 32%;
Overall Acceptance Rate 273 of 785 submissions, 35%

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  • (2019)Partial-Gated Memristor Crossbar for Fast and Power-Efficient Defect-Tolerant TrainingMicromachines10.3390/mi1004024510:4(245)Online publication date: 13-Apr-2019

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