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Model-driven design & synthesis of the SHA-256 cryptographic hash function in ReWire

Published: 01 October 2016 Publication History

Abstract

There are many algorithms whose implementations can benefit both from hardware acceleration and formal verification and we would like to develop high assurance implementations as rapidly as possible. Critical computing infrastructure like cryptographic algorithms are prime candidates both for such acceleration and for formal verification. We show how to derive a verifiable, hardware-accelerated implementation of the SHA-256 cryptographic hash in the ReWire functional hardware description language in which the hardware-software partitioning of the implementation is reflected in the type system itself.

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Cited By

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  • (2020)A High-Performance Parallel Hardware Architecture of SHA-256 Hash in ASIC2020 22nd International Conference on Advanced Communication Technology (ICACT)10.23919/ICACT48636.2020.9061457(1242-1247)Online publication date: Feb-2020
  • (2019)A High-Performance Parallel Computation Hardware Architecture in ASIC of SHA-256 Hash2019 21st International Conference on Advanced Communication Technology (ICACT)10.23919/ICACT.2019.8701906(52-55)Online publication date: Feb-2019
  • (2019)The Mechanized Marriage of Effects and Monads with Applications to High-assurance HardwareACM Transactions on Embedded Computing Systems10.1145/327428218:1(1-26)Online publication date: 8-Jan-2019
  • Show More Cited By

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Published In

cover image ACM Conferences
RSP '16: Proceedings of the 27th International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype
October 2016
141 pages
ISBN:9781450345354
DOI:10.1145/2990299
Publication rights licensed to ACM. ACM acknowledges that this contribution was authored or co-authored by an employee, contractor or affiliate of the United States government. As such, the Government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for Government purposes only.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 October 2016

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Author Tags

  1. functional programming
  2. high-level synthesis

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  • Research-article

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ESWEEK'16
Sponsor:
ESWEEK'16: TWELFTH EMBEDDED SYSTEM WEEK
October 1 - 7, 2016
Pennsylvania, Pittsburgh

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View all
  • (2020)A High-Performance Parallel Hardware Architecture of SHA-256 Hash in ASIC2020 22nd International Conference on Advanced Communication Technology (ICACT)10.23919/ICACT48636.2020.9061457(1242-1247)Online publication date: Feb-2020
  • (2019)A High-Performance Parallel Computation Hardware Architecture in ASIC of SHA-256 Hash2019 21st International Conference on Advanced Communication Technology (ICACT)10.23919/ICACT.2019.8701906(52-55)Online publication date: Feb-2019
  • (2019)The Mechanized Marriage of Effects and Monads with Applications to High-assurance HardwareACM Transactions on Embedded Computing Systems10.1145/327428218:1(1-26)Online publication date: 8-Jan-2019
  • (2017)The Verification of SHA-256 IP using a semi-automatic UVM platform2017 13th IEEE International Conference on Electronic Measurement & Instruments (ICEMI)10.1109/ICEMI.2017.8265733(111-115)Online publication date: Oct-2017

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