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POSTER: Fault-tolerant Execution on COTS Multi-core Processors with Hardware Transactional Memory Support

Authors:

Youfeng WuAuthors Info & Claims

PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and Compilation

Pages 421 - 422

https://doi.org/10.1145/2967938.2974051

Published: 11 September 2016 Publication History

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Abstract

Software-based fault-tolerance mechanisms can increase the reliability of multi-core CPUs while being cheaper and more flexible than hardware solutions like lockstep architectures. However, checkpoint creation, error detection and correction entail high performance overhead if implemented in software. We propose a software/hardware hybrid approach, which leverages Intel's hardware transactional memory (TSX) to support implicit checkpoint creation and fast rollback. Hardware enhancements are proposed and evaluated, leading to a resulting performance overhead of 19% on average.

References

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F. Haas, S. Weis, S. Metzlaff, and T. Ungerer. Exploiting Intel TSX for Fault-Tolerant Execution in Safety-Critical Systems. In Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pages 197--202, 2014.

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P. Hammarlund, A. J. Martinez, A. A. Bajwa, D. L. Hill, E. Hallnor, et al. Haswell: The Fourth-Generation Intel Core Processor. IEEE Micro, 34(2):6--20, 2014.

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A. Shye, J. Blomstedt, T. Moseley, V. J. Reddi, and D. A. Connors. PLR: A Software Approach to Transient Fault Tolerance for Multicore Architectures. IEEE Transactions on Dependable and Secure Computing (TDSC), 6(2):135--148, 2009.

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Cited By

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Haas FWeis SUngerer TPokam GWu Y(2017)Fault-Tolerant Execution on COTS Multi-core Processors with Hardware Transactional Memory SupportArchitecture of Computing Systems - ARCS 201710.1007/978-3-319-54999-6_2(16-30)Online publication date: 4-Mar-2017
https://doi.org/10.1007/978-3-319-54999-6_2

Index Terms

POSTER: Fault-tolerant Execution on COTS Multi-core Processors with Hardware Transactional Memory Support
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Multicore architectures
  2. Dependable and fault-tolerant systems and networks
    1. Redundancy
2. Hardware
  1. Robustness

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Information & Contributors

Information

Published In

PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and Compilation

September 2016

474 pages

ISBN:9781450341219

DOI:10.1145/2967938

General Chairs:
Ayal Zaks
Intel, Israel
,
Bilha Mendelson
Optitura, Israel
,
Program Chairs:
Lawrence Rauchwerger
Texas A&M University, USA
,
Wen-mei W. Hwu
University of Illinois at Urbana-Champaign, USA

Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 11 September 2016

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PACT '16

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IFIP WG 10.3
IEEE TCCA
SIGARCH
IEEE CS TCPP

PACT '16: International Conference on Parallel Architectures and Compilation

September 11 - 15, 2016

Haifa, Israel

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PACT '16 Paper Acceptance Rate 31 of 119 submissions, 26%;

Overall Acceptance Rate 121 of 471 submissions, 26%

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Haas FWeis SUngerer TPokam GWu Y(2017)Fault-Tolerant Execution on COTS Multi-core Processors with Hardware Transactional Memory SupportArchitecture of Computing Systems - ARCS 201710.1007/978-3-319-54999-6_2(16-30)Online publication date: 4-Mar-2017
https://doi.org/10.1007/978-3-319-54999-6_2

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Hybrid STM/HTM for nested transactions on OpenJDK