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Making neural encoding robust and energy efficient: An advanced analog temporal encoder for brain-inspired computing systems

Published: 07 November 2016 Publication History

Abstract

Neural encoder is one of the key components in neuromorphic computing systems, whereby sensory information is transformed into spike coded trains. The design of temporal encoder has attracted a widespread attention in the field of neuromorphic computing in the past few years. The information in the temporal encoding scheme with inter-spike intervals can arise from correlations between spike times, which could not be incorporated in the traditional rate encoding scheme. In this paper, we propose a robust and energy efficient analog implementation of the spiking temporal encoder. We pattern the neural activities across multiple timescales and encode the sensory information using time dependent temporal scales. The concept of iteration structure is introduced to construct a neural encoder that greatly increases the information process ability of the proposed temporal encoder. Integrated with iteration technique and operational-amplifier-free design, the error rate of the output temporal codes is reduced to an extremely low level. A lower sampling rate accompanied by additional verification spikes is introduced in the schemes, which significantly reduces the power consumption of the encoding system. To the best of our knowledge, our proposed neuron circuit is the first analog hardware implementation of the neural encoder that could present the sensory data using inter-spike interval temporal encoding scheme. The simulation and measurement results show the proposed temporal encoder exhibits not only energy efficiency but also high accuracy.

7. References

[1]
D. Monroe, “Neuromorphic computing gets ready for the (really) big time”, Commun. ACM, vol. 57, no. 6, pp. 13–15, 2014.
[2]
R. Ananthanarayanan, S. K. Esser, H. D. Simon, and D. S. Modha, “The cat is out of the bag: cortical simulations with 109 neurons, 1013 synapses”, Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis, pp. 1–12, 2009.
[3]
P. A. Merolla, J. V. Arthur, R. Alvarez-Icaza, A. S. Cassidy, J. Sawada, F. Akopyan, B. L. Jackson, N. Imam, C. Guo, Y. Nakamura, B. Brezzo, I. Vo, S. K. Esser, R. Appuswamy, B. Taba, A. Amir, M. D. Flickner, W. P. Risk, R. Manohar, and D. S. Modha, “Artificial brains. A million spiking-neuron integrated circuit with a scalable communication network and interface”, Science, vol. 345, no. 6197, pp. 668–73, 2014.
[4]
S. Yu, Y. Wu, R. Jeyasingh, D. Kuzum, and H. S. P. Wong, “An Electronic Synapse Device Based on Metal Oxide Resistive Switching Memory for Neuromorphic Computation”, IEEE Transactions on Electron Devices, vol. 58, no. 8, pp. 2729–2737, 2011.
[5]
P. Lennie, “The cost of cortical computation”, Curr Biol, vol. 13, no. 6, pp. 493–7, 2003.
[6]
D. S. Reich, F. Mechler, K. P. Purpura, and J. D. Victor, “Interspike intervals, receptive fields, and information encoding in primary visual cortex”, J Neurosci, vol. 20, no. 5, pp. 1964–74, 2000.
[7]
R. Brasselet, S. Panzeri, N. K. Logothetis, and C. Kayser, “Neurons with stereotyped and rapid responses provide a reference frame for relative temporal coding in primate auditory cortex”, J Neurosci, vol. 32, no. 9, pp. 2998–3008, 2012.
[8]
L. Shao, X. Zhen, D. Tao, and X. Li, “Spatio-Temporal Laplacian Pyramid Coding for Action Recognition”, IEEE Transactions on Cybernetics, vol. 44, no. 6, pp. 817–827, 2014.
[9]
A. A. Grace, and B. S. Bunney, “The control of firing pattern in nigral dopamine neurons: single spike firing”, J Neurosci, vol. 4, no. 11, pp. 2866–76, 1984.
[10]
J. Luthman, F. E. Hoebeek, R. Maex, N. Davey, R. Adams, C. I. De Zeeuw, and V. Steuber, “STD-dependent and independent encoding of input irregularity as spike rate in a computational model of a cerebellar nucleus neuron”, Cerebellum, vol. 10, no. 4, pp. 667–82, 2011.
[11]
A. Joubert, B. Belhadj, O. Temam, H. R, x00E, and liot, “Hardware spiking neurons design: Analog or digital?”, The 2012 International Joint Conference on Neural Networks (IJCNN), pp. 1–5, 2012.
[12]
C. Zhao, B. T. Wysocki, Y. Liu, C. D. Thiem, N. R. McDonald, and Y. Yi, “Spike-Time-Dependent Encoding for Neuromorphic Processors”, ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 12, no. 3, pp. 23, 2015.
[13]
C. Zhao, W. Danesh, B. T. Wysocki, and Y. Yi, “Neuromorphic encoding system design with chaos based CMOS analog neuron”, Computational Intelligence for Security and Defense Applications (CISDA), 2015 IEEE Symposium on IEEE, 2015.
[14]
I. E. Ebong, and P. Mazumder, “CMOS and Memristor-Based Neural Network Design for Position Detection”, Proceedings of the IEEE, vol. 100, no. 6, pp. 2050–2060, 2012.
[15]
Y. Kim, Y. Zhang, and P. Li, “A digital neuromorphic VLSI architecture with memristor crossbar synaptic array for machine learning”, SOC Conference (SOCC), 2012 IEEE International, pp. 328–333, 2012.
[16]
J. S. Seo, and M. Seok, “Digital CMOS neuromorphic processor design featuring unsupervised online learning”, 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 49–51, 2015.
[17]
C. Piguet, “Low-Power CMOS Circuits: Technology, Logic Design and CAD Tools”, CRC Press, 2005.

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  • (2023)Enabling a New Methodology of Neural Coding: Multiplexing Temporal Encoding in Neuromorphic ComputingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.323451431:3(331-342)Online publication date: Mar-2023
  • (2023)Encoding integers and rationals on neuromorphic computers using virtual neuronScientific Reports10.1038/s41598-023-35005-x13:1Online publication date: 6-Jul-2023
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        2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
        Nov 2016
        946 pages

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        IEEE Press

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        Published: 07 November 2016

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        • (2023)Spiking Neural Encoding and Hardware Implementations for Neuromorphic ComputingNeuromorphic Computing10.5772/intechopen.113050Online publication date: 15-Nov-2023
        • (2023)Enabling a New Methodology of Neural Coding: Multiplexing Temporal Encoding in Neuromorphic ComputingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.323451431:3(331-342)Online publication date: Mar-2023
        • (2023)Encoding integers and rationals on neuromorphic computers using virtual neuronScientific Reports10.1038/s41598-023-35005-x13:1Online publication date: 6-Jul-2023
        • (2022)Review of Closed-Loop Brain–Machine Interface Systems From a Control PerspectiveIEEE Transactions on Human-Machine Systems10.1109/THMS.2021.313867752:5(877-893)Online publication date: Oct-2022
        • (2022)Virtual Neuron: A Neuromorphic Approach for Encoding Numbers2022 IEEE International Conference on Rebooting Computing (ICRC)10.1109/ICRC57508.2022.00017(100-105)Online publication date: Dec-2022
        • (2021)Low-power Analog and Mixed-signal IC Design of Multiplexing Neural Encoder in Neuromorphic Computing2021 22nd International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED51717.2021.9424267(154-159)Online publication date: 7-Apr-2021
        • (2020)Quantized Neural Networks and Neuromorphic Computing for Embedded SystemsIntelligent System and Computing [Working Title]10.5772/intechopen.91835Online publication date: 30-Mar-2020
        • (2020)Encoding, model, and architectureProceedings of the 39th International Conference on Computer-Aided Design10.1145/3400302.3415608(1-9)Online publication date: 2-Nov-2020
        • (2019)Opening the “Black Box” of Silicon Chip Design in Neuromorphic ComputingBio-Inspired Technology [Working Title]10.5772/intechopen.83832Online publication date: 8-Mar-2019
        • (2019)Design and Analysis of Real Time Spiking Neural Network Decoder for Neuromorphic ChipsProceedings of the International Conference on Neuromorphic Systems10.1145/3354265.3354280(1-4)Online publication date: 23-Jul-2019
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