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Silent Shredder: Zero-Cost Shredding for Secure Non-Volatile Main Memory Controllers

Authors:

Pratyusa Manadhata,

William HorneAuthors Info & Claims

ACM SIGPLAN Notices, Volume 51, Issue 4

Pages 263 - 276

https://doi.org/10.1145/2954679.2872377

Published: 25 March 2016 Publication History

Abstract

As non-volatile memory (NVM) technologies are expected to replace DRAM in the near future, new challenges have emerged. For example, NVMs have slow and power-consuming writes, and limited write endurance. In addition, NVMs have a data remanence vulnerability, i.e., they retain data for a long time after being powered off. NVM encryption alleviates the vulnerability, but exacerbates the limited endurance by increasing the number of writes to memory. We observe that, in current systems, a large percentage of main memory writes result from data shredding in operating systems, a process of zeroing out physical pages before mapping them to new processes, in order to protect previous processes' data. In this paper, we propose Silent Shredder, which repurposes initialization vectors used in standard counter mode encryption to completely eliminate the data shredding writes. Silent Shredder also speeds up reading shredded cache lines, and hence reduces power consumption and improves overall performance. To evaluate our design, we run three PowerGraph applications and 26 multi-programmed workloads from the SPEC 2006 suite, on a gem5-based full system simulator. Silent Shredder eliminates an average of 48.6% of the writes in the initialization and graph construction phases. It speeds up main memory reads by 3.3 times, and improves the number of instructions per cycle (IPC) by 6.4% on average. Finally, we discuss several use cases, including virtual machines' data isolation and user-level large data initialization, where Silent Shredder can be used effectively at no extra cost.

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Index Terms

Silent Shredder: Zero-Cost Shredding for Secure Non-Volatile Main Memory Controllers
1. Computer systems organization
  1. Architectures
    1. Parallel architectures

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Information & Contributors

Information

Published In

cover image ACM SIGPLAN Notices

ACM SIGPLAN Notices Volume 51, Issue 4

ASPLOS '16

April 2016

774 pages

ISSN:0362-1340

EISSN:1558-1160

DOI:10.1145/2954679

Editor:
Andy Gill
University of Kansas, Lawrence, KS

Issue’s Table of Contents

ASPLOS '16: Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems
March 2016
824 pages
ISBN:9781450340915
DOI:10.1145/2872362
General Chair:
Tom Conte
Georgia Tech, USA
,
Program Chair:
Yuanyuan Zhou
University of California, San Diego, USA

Copyright © 2016 ACM.

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Published: 25 March 2016

Published in SIGPLAN Volume 51, Issue 4

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Cited By

Nath AKapoor H(2024)AmLuCEP: Amalgamating LUT-based Compression and Adaptive Encoding Assisted Block Placement To Improve Lifetime of PCM-based Main MemoriesACM Transactions on Design Automation of Electronic Systems10.1145/368933429:6(1-24)Online publication date: 20-Aug-2024
https://dl.acm.org/doi/10.1145/3689334
Shadab RZou YGandham SAwad ALin M(2024)A Secure Computing System With Hardware-Efficient Lazy Bonsai Merkle Tree for FPGA-Attached Embedded MemoryIEEE Transactions on Dependable and Secure Computing10.1109/TDSC.2023.332493521:4(3262-3279)Online publication date: 1-Jul-2024
https://dl.acm.org/doi/10.1109/TDSC.2023.3324935
Zubair KAbdullah RMohaisen DAwad A(2024)RC-NVM: Recovery-Aware Reliability-Security Co-Design for Non-Volatile MemoriesIEEE Transactions on Dependable and Secure Computing10.1109/TDSC.2023.327903121:4(1817-1830)Online publication date: 1-Jul-2024
https://dl.acm.org/doi/10.1109/TDSC.2023.3279031
Zou MZhu ZGreenberg-Toledo TLeitersdorf OLi JZhou JWang YDu NKvatinsky S(2024)TDPP: 2-D Permutation-Based Protection of Memristive Deep Neural NetworksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.332235143:3(742-755)Online publication date: 1-Mar-2024
https://dl.acm.org/doi/10.1109/TCAD.2023.3322351
Shadab RZou YLin M(2024)CTR+: A High-Performance Metadata Access Scheme for Secure Embedded Memory in Heterogeneous Computing Systems2024 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)10.1109/HOST55342.2024.10545394(304-308)Online publication date: 6-May-2024
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Nath AKapoor HSavidis ISasan AThapliyal HDeMara R(2022)CoSeP: Compression and Content-based Selection Procedure to Improve Lifetime of Encrypted Non-Volatile Main MemoriesProceedings of the Great Lakes Symposium on VLSI 202210.1145/3526241.3530375(393-396)Online publication date: 6-Jun-2022
https://dl.acm.org/doi/10.1145/3526241.3530375
Zou YZubair KAlwadi MShadab RGandham SAwad ALin M(2022)ARES: Persistently Secure Non-Volatile Memory with Processor-transparent and Hardware-friendly Integrity Verification and Metadata RecoveryACM Transactions on Embedded Computing Systems10.1145/349273521:1(1-32)Online publication date: 10-Feb-2022
https://dl.acm.org/doi/10.1145/3492735
Nath AKapoor H(2022) Pop-Crypt: Identification and Management of Pop ular Words for Enhancing Lifetime of En Crypt ed Nonvolatile Main Memories IEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2022.318379330:9(1219-1229)Online publication date: Sep-2022
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Xie ZHan YChen X(2022)PME: Processing-in-memory Masking and Encoding for Secure NVM2022 IEEE 24th Int Conf on High Performance Computing & Communications; 8th Int Conf on Data Science & Systems; 20th Int Conf on Smart City; 8th Int Conf on Dependability in Sensor, Cloud & Big Data Systems & Application (HPCC/DSS/SmartCity/DependSys)10.1109/HPCC-DSS-SmartCity-DependSys57074.2022.00231(1501-1508)Online publication date: Dec-2022
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Di BHu DXie ZSun JChen HRen JLi D(2021)TLB-pilot: Mitigating TLB Contention Attack on GPUs with Microarchitecture-Aware SchedulingACM Transactions on Architecture and Code Optimization10.1145/349121819:1(1-23)Online publication date: 6-Dec-2021
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