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Implementation of precise interrupts in pipelined processors

Authors:

James E. Smith,

Andrew R. PleszkunAuthors Info & Claims

ISCA '98: 25 years of the international symposia on Computer architecture (selected papers)

Pages 291 - 299

https://doi.org/10.1145/285930.285988

Published: 01 August 1998 Publication History

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Mohamed AEl-Moursy AFahmy H(2015)Real-Time Memory Controller for Embedded Multi-core SystemProceedings of the 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conf on Embedded Software and Systems10.1109/HPCC-CSS-ICESS.2015.133(839-842)Online publication date: 24-Aug-2015
https://dl.acm.org/doi/10.1109/HPCC-CSS-ICESS.2015.133
Yazdanpanah FAlvarez-Martinez CJimenez-Gonzalez DEtsion Y(2014)Hybrid Dataflow/von-Neumann ArchitecturesIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2013.12525:6(1489-1509)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1109/TPDS.2013.125
Rodrigues RKundu SKhan O(2010)Shadow checker (SC): A low-cost hardware scheme for online detection of faults in small memory structures of a microprocessor2010 IEEE International Test Conference10.1109/TEST.2010.5699222(1-10)Online publication date: Nov-2010
https://doi.org/10.1109/TEST.2010.5699222
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Implementation of precise interrupts in pipelined processors

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Interrupts and in particular precise interrupts constitute an integral part of all computer architectures. Implementing precise interrupts can substantially inhibit the performance of computers. To gain some insight into the problem, we divide common ...
A Mechanism for Implementing Precise Exceptions in Pipelined Processors
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An exception is precise if all instructions before the faulting instruction have completed and those instructions following it can be restarted from scratch. If all exceptions in a processor are precise, the processor is said to implement the precise ...

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Published In

ISCA '98: 25 years of the international symposia on Computer architecture (selected papers)

August 1998

546 pages

ISBN:1581130589

DOI:10.1145/285930

Editor:
Gurindar S. Sohi
Univ. of Wisconsin-Madison, Madison

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 01 August 1998

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ISCA98: International Symposium on Computer Architecture

June 27 - July 2, 1998

Barcelona, Spain

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Overall Acceptance Rate 543 of 3,203 submissions, 17%

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Cited By

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Mohamed AEl-Moursy AFahmy H(2015)Real-Time Memory Controller for Embedded Multi-core SystemProceedings of the 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conf on Embedded Software and Systems10.1109/HPCC-CSS-ICESS.2015.133(839-842)Online publication date: 24-Aug-2015
https://dl.acm.org/doi/10.1109/HPCC-CSS-ICESS.2015.133
Yazdanpanah FAlvarez-Martinez CJimenez-Gonzalez DEtsion Y(2014)Hybrid Dataflow/von-Neumann ArchitecturesIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2013.12525:6(1489-1509)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1109/TPDS.2013.125
Rodrigues RKundu SKhan O(2010)Shadow checker (SC): A low-cost hardware scheme for online detection of faults in small memory structures of a microprocessor2010 IEEE International Test Conference10.1109/TEST.2010.5699222(1-10)Online publication date: Nov-2010
https://doi.org/10.1109/TEST.2010.5699222
Mutlu OMoscibroda T(2009)Parallelism-Aware Batch SchedulingIEEE Micro10.1109/MM.2009.1229:1(22-32)Online publication date: 1-Jan-2009
https://dl.acm.org/doi/10.1109/MM.2009.12
Yourst MGhose K(2005)Incremental Commit Groups for Non-Atomic Trace Processing38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05)10.1109/MICRO.2005.23(67-80)Online publication date: 2005
https://doi.org/10.1109/MICRO.2005.23
Liu Zhenyu Qi Jiayue (2003)Implementation of precise exception in a 5-stage pipeline embedded processor2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-0310.1109/ICASIC.2003.1277582(447-451 Vol.1)Online publication date: 2003
https://doi.org/10.1109/ICASIC.2003.1277582

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Implementing Precise Interrupts in Pipelined Processors

Precise Interrupts

A Mechanism for Implementing Precise Exceptions in Pipelined Processors