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A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms

Authors:

Juan Antonio Clemente,

Donatella SciutoAuthors Info & Claims

ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 7, Issue 2

Article No.: 9, Pages 1 - 27

https://doi.org/10.1145/2611562

Published: 04 July 2014 Publication History

Abstract

Reconfigurable platforms are a promising technology that offers an interesting trade-off between flexibility and performance, which many recent embedded system applications demand, especially in fields such as multimedia processing. These applications typically involve multiple ad-hoc tasks for hardware acceleration, which are usually represented using formalisms such as Data Flow Diagrams (DFDs), Data Flow Graphs (DFGs), Control and Data Flow Graphs (CDFGs) or Petri Nets. However, none of these models is able to capture at the same time the pipeline behavior between tasks (that therefore can coexist in order to minimize the application execution time), their communication patterns, and their data dependencies. This article proves that the knowledge of all this information can be effectively exploited to reduce the resource requirements and the timing performance of modern reconfigurable systems, where a set of hardware accelerators is used to support the computation. For this purpose, this article proposes a novel task representation model, named Temporal Constrained Data Flow Diagram (TCDFD), which includes all this information. This article also presents a mapping-scheduling algorithm that is able to take advantage of the new TCDFD model. It aims at minimizing the dynamic reconfiguration overhead while meeting the communication requirements among the tasks. Experimental results show that the presented approach achieves up to 75% of resources saving and up to 89% of reconfiguration overhead reduction with respect to other state-of-the-art techniques for reconfigurable platforms.

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Cited By

Sharma DKirischian L(2021)A Decision-Making Method Providing Sustainability to FPGA-Based SoCs by Run-Time Structural Adaptation to Mode of Operation, Power Budget, and Die Temperature VariationsInternational Journal of Reconfigurable Computing10.1155/2021/55129382021Online publication date: 1-Jan-2021
https://dl.acm.org/doi/10.1155/2021/5512938
Wang ZTang QGuo BWei JWang L(2020)Resource Partitioning and Application Scheduling with Module Merging on Dynamically and Partially Reconfigurable FPGAsElectronics10.3390/electronics90914619:9(1461)Online publication date: 7-Sep-2020
https://doi.org/10.3390/electronics9091461
Tang QGuo BWang Z(2020)Sw/Hw Partitioning and Scheduling on Region-Based Dynamic Partial Reconfigurable System-on-ChipElectronics10.3390/electronics90913629:9(1362)Online publication date: 21-Aug-2020
https://doi.org/10.3390/electronics9091362
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Index Terms

A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms
1. Computer systems organization

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Published In

cover image ACM Transactions on Reconfigurable Technology and Systems

ACM Transactions on Reconfigurable Technology and Systems Volume 7, Issue 2

June 2014

199 pages

ISSN:1936-7406

EISSN:1936-7414

DOI:10.1145/2638850

Issue’s Table of Contents

Copyright © 2014 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 04 July 2014

Accepted: 01 November 2013

Revised: 01 August 2013

Received: 01 February 2013

Published in TRETS Volume 7, Issue 2

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Ministerio de Educación, Cultura y Deporte
Seventh Framework Programme
Nano-Tera.ch with Swiss Confederation financing
Swiss National Science Foundation
ObeSense RTD

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Cited By

Sharma DKirischian L(2021)A Decision-Making Method Providing Sustainability to FPGA-Based SoCs by Run-Time Structural Adaptation to Mode of Operation, Power Budget, and Die Temperature VariationsInternational Journal of Reconfigurable Computing10.1155/2021/55129382021Online publication date: 1-Jan-2021
https://dl.acm.org/doi/10.1155/2021/5512938
Wang ZTang QGuo BWei JWang L(2020)Resource Partitioning and Application Scheduling with Module Merging on Dynamically and Partially Reconfigurable FPGAsElectronics10.3390/electronics90914619:9(1461)Online publication date: 7-Sep-2020
https://doi.org/10.3390/electronics9091461
Tang QGuo BWang Z(2020)Sw/Hw Partitioning and Scheduling on Region-Based Dynamic Partial Reconfigurable System-on-ChipElectronics10.3390/electronics90913629:9(1362)Online publication date: 21-Aug-2020
https://doi.org/10.3390/electronics9091362
Tang QWang ZGuo BZhu LWei J(2020)Partitioning and Scheduling with Module Merging on Dynamic Partial Reconfigurable FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/340370213:3(1-24)Online publication date: 21-Aug-2020
https://dl.acm.org/doi/10.1145/3403702
Ghavidel ASedaghat YNaghibzadeh M(2019)Hybrid scheduling to enhance reliability of real-time tasks running on reconfigurable devicesThe Journal of Supercomputing10.1007/s11227-019-02976-676:6(4701-4730)Online publication date: 27-Aug-2019
https://dl.acm.org/doi/10.1007/s11227-019-02976-6
Sharma DKirischian LKirischian V(2018)Run-Time Mitigation of Power Budget Variations and Hardware Faults by Structural Adaptation of FPGA-Based Multi-Modal SoPCComputers10.3390/computers70400527:4(52)Online publication date: 11-Oct-2018
https://doi.org/10.3390/computers7040052
Ramezani RSedaghat YNaghibzadeh MClemente J(2017)Reliability and Makespan Optimization of Hardware Task Graphs in Partially Reconfigurable PlatformsIEEE Transactions on Aerospace and Electronic Systems10.1109/TAES.2017.266733853:2(983-994)Online publication date: Apr-2017
https://doi.org/10.1109/TAES.2017.2667338
Mishra AAgarwal MAsati ARaju K(2017)Using graph isomorphism for mapping of data flow applications on reconfigurable computing systemsMicroprocessors and Microsystems10.1016/j.micpro.2016.12.00851(343-355)Online publication date: Jun-2017
https://doi.org/10.1016/j.micpro.2016.12.008
Khan MShafique MHenkel JKhan MShafique MHenkel J(2017)Background and Related WorkEnergy Efficient Embedded Video Processing Systems10.1007/978-3-319-61455-7_2(25-65)Online publication date: 19-Sep-2017
https://doi.org/10.1007/978-3-319-61455-7_2
Khan MShafique MHenkel JNebel WAtienza D(2015)Power-efficient accelerator allocation in adaptive dark silicon many-core systemsProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2757025(916-919)Online publication date: 9-Mar-2015
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