More Web Proxy on the site http://driver.im/

research-article

Improving ESL power models using switching activity information from timed functional models

Authors:

Stefan Schürmans,

Diandian Zhang,

Rainer Leupers,

Xiaotao ChenAuthors Info & Claims

SCOPES '14: Proceedings of the 17th International Workshop on Software and Compilers for Embedded Systems

Pages 89 - 97

https://doi.org/10.1145/2609248.2609250

Published: 10 June 2014 Publication History

Abstract

Early design space exploration at Electronic System Level (ESL) can be done either using untimed functional models, timed functional models or performance models, which use random or zero data instead of the actual data. In order to be applicable to the two latter types, ESL power estimation approaches often rely only on sub-block activity information. This work shows the benefit of additionally using the switching activity information of actual data available in timed functional models for power estimation. A case study shows that a considerable gain in accuracy can be achieved while causing only a moderate simulation slowdown.

References

[1]

Cadence digital implementation. {Online} http://www.cadence.com/products/di/ (accessed 03/2014).

[2]

Docea Aceplorer. {Online} http://www.doceapower.com/products-services/aceplorer.html (accessed 03/2014).

[3]

Synopsys tools. {Online} http://synopsys.com/Tools (accessed 03/2014).

[4]

SystemC. {Online} http://www.accellera.org/downloads/standards/systemc (accessed 03/2014).

[5]

D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A framework for architectural-level power analysis and optimizations. In Proceedings of the 27th Annual International Symposium on Computer Architecture, ISCA '00, New York, NY, USA, 2000. ACM.

Digital Library

[6]

J. W. Eaton, D. Bateman, and S. Hauberg. GNU Octave version 3.0.1 manual: a high-level interactive language for numerical computations. CreateSpace Independent Publishing Platform, 2009.

[7]

L. Eeckhout and K. D. Bosschere. Early design phase power/performance modeling through statistical simulation. In Proceedings of the 2001 IEEE International Symposium on Performance Analysis of Systems and Software. IEEE, 2001.

[8]

T. Givargis, F. Vahid, and J. Henkel. Instruction-based system-level power evaluation of system-on-a-chip peripheral cores. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 10(6):856--863, Dec 2002.

Digital Library

[9]

K. Grüttner, K. Hylla, S. Rosinger, and W. Nebel. Towards an ESL framework for timing and power aware rapid prototyping of HW/SW systems. In Specification Design Languages (FDL 2010), 2010 Forum on, Sep. 2010.

[10]

R. W. Hamming. Error detecting and error correcting codes. Bell System Technical Journal, 29:147--160, 1950.

[11]

N. Julien, J. Laurent, E. Senn, and E. Martin. Power consumption modeling and characterization of the TI C6201. Micro, IEEE, 23(5), Sep. 2003.

Digital Library

[12]

M. Jung, C. Weis, P. Bertram, and N. Wehn. Power modelling of 3D-stacked memories with TLM2.0 based virtual platforms. In Synopsys User Group Conference (SNUG), Munich, Germany, May 2013.

[13]

J. Laurent, N. Julien, E. Senn, and E. Martin. Functional level power analysis: An efficient approach for modeling the power consumption of complex processors. In Proceedings of the Conference on Design, Automation and Test in Europe, DATE '04, Washington, DC, USA, 2004. IEEE Computer Society.

Digital Library

[14]

L. Ost, G. Guindani, F. Moraes, L. Indrusiak, and S. Määttä. Exploring NoC-based MPSoC design space with power estimation models. IEEE Design and Test, 28, Mar. 2011.

Digital Library

[15]

S. Pasricha, Y.-H. Park, F. Kurdahi, and N. Dutt. System-level power-performance trade-offs in bus matrix communication architecture synthesis. In Hardware/Software Codesign and System Synthesis, 2006. CODES+ISSS '06. Proceedings of the 4th International Conference, Oct 2006.

Digital Library

[16]

S. K. Rethinagiri, R. ben Atitallah, and J.-L. Dekeyser. A system level power consumption estimation for MPSoC. In 2011 International Symposium on System on Chip. IEEE, Nov. 2011.

[17]

S. Schürmans, D. Zhang, D. Auras, R. Leupers, G. Ascheid, X. Chen, and L. Wang. Creation of ESL power models for communication architectures using automatic calibration. In Proceedings of the 50th Annual Design Automation Conference, DAC '13, New York, NY, USA, 2013. ACM.

Digital Library

[18]

M. Streubühr, R. Rosales, R. Hasholzner, C. Haubelt, and J. Teich. ESL power and performance estimation for heterogeneous MPSoCs using SystemC. In Specification and Design Languages (FDL), 2011 Forum on, Sept 2011.

[19]

V. Tiwari, S. Malik, and A. Wolfe. Power analysis of embedded software: A first step towards software power minimization. Very Large Scale Integration Systems, IEEE Transactions on, 2(4), Dec. 1994.

Digital Library

[20]

C. Trabelsi, R. ben Atitallah, S. Meftali, J.-L. Dekeyser, and A. Jemai. A model-driven approach for hybrid power estimation in embedded systems design. EURASIP Journal on Embedded Systems, 2011.

[21]

N. Vijaykrishnan, M. Kandemir, M. J. Irwin, H. S. Kim, and W. Ye. The design and use of SimplePower: A cycle-accurate energy estimation tool. In Proceedings of the 37th Annual Design Automation Conference, DAC '00, New York, NY, USA, 2000. ACM.

Digital Library

Cited By

Chen SChen JWang L(2018)A Chip-Level Anti-Reverse Engineering TechniqueACM Journal on Emerging Technologies in Computing Systems10.1145/317346214:2(1-20)Online publication date: 25-Jul-2018
https://dl.acm.org/doi/10.1145/3173462
Bucher HKlimm ASander OBecker J(2015)Power Estimation of an ECDSA Core applied in V2X Scenarios using Heterogeneous Distributed SimulationProceedings of the 19th International Symposium on Distributed Simulation and Real Time Applications10.1109/DS-RT.2015.35(187-194)Online publication date: 14-Oct-2015
https://dl.acm.org/doi/10.1109/DS-RT.2015.35

Index Terms

Improving ESL power models using switching activity information from timed functional models
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
      1. Modeling methodologies
2. Hardware
  1. Hardware validation

Recommendations

Creation of ESL power models for communication architectures using automatic calibration
DAC '13: Proceedings of the 50th Annual Design Automation Conference

Power consumption is an important factor in chip design. The fundamental design decisions drawn during early design space exploration at electronic system level (ESL) have a large impact on the power consumption. This requires to estimate power already ...
Frequency-Aware ESL Power Estimation for ARM Cortex-A9 Using a Black Box Processor Model
Special Issue on VIPES, Special Issue on ICESS2015 and Regular Papers

Power estimation has become a strongly desired feature in Electronic System Level (ESL) simulations. Most existing power estimation approaches for this abstraction level require component models with observable internals. However, most ESL models of ...
ESL Black Box Power Estimation: Automatic Calibration for IEEE UPF 3.0 Power Models
RAPIDO '18: Proceedings of the Rapido'18 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools

Power-aware design space exploration at early electronic system level (ESL) is highly facilitated by virtual platforms. In order to define and exchange power models, the IEEE standard 1801-2015 -- UPF has been defined to allow developers, vendors and ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Other conferences

SCOPES '14: Proceedings of the 17th International Workshop on Software and Compilers for Embedded Systems

June 2014

162 pages

ISBN:9781450329415

DOI:10.1145/2609248

General Chair:
Henk Corporaal
Eindhoven University of Technology, NL
,
Program Chair:
Sander Stuijk
Eindhoven University of Technology, NL

Copyright © 2014 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

EDAA: European Design Automation Association

In-Cooperation

SIGBED: ACM Special Interest Group on Embedded Systems

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 June 2014

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Funding Sources

Seventh Framework Programme

Conference

SCOPES '14

Sponsor:

EDAA

SCOPES '14: 17th International Workshop on Software and Compilers for Embedded Systems

June 10 - 11, 2014

Sankt Goar, Germany

Acceptance Rates

Overall Acceptance Rate 38 of 79 submissions, 48%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

2
Total Citations
View Citations
140
Total Downloads

Downloads (Last 12 months)2
Downloads (Last 6 weeks)0

Reflects downloads up to 11 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

Chen SChen JWang L(2018)A Chip-Level Anti-Reverse Engineering TechniqueACM Journal on Emerging Technologies in Computing Systems10.1145/317346214:2(1-20)Online publication date: 25-Jul-2018
https://dl.acm.org/doi/10.1145/3173462
Bucher HKlimm ASander OBecker J(2015)Power Estimation of an ECDSA Core applied in V2X Scenarios using Heterogeneous Distributed SimulationProceedings of the 19th International Symposium on Distributed Simulation and Real Time Applications10.1109/DS-RT.2015.35(187-194)Online publication date: 14-Oct-2015
https://dl.acm.org/doi/10.1109/DS-RT.2015.35

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents