A new approach for partitioning VLSI circuits on transistor level
Abstract
For parallel simulation of VLSI circuits on transistor level a sophisticated partitioning of the circuits into subcircuits is crucial. Each net connecting the subcircuits causes additional communication and computation effort. As the slave processors simulating the subcircuits advance synchronously in time, the computation effort for each subcircuit should be approximately the same. In this paper a new approach for partitioning VLSI circuits on transistor level yielding a low number of interconnects between the subcircuits and balanced subcircuit sizes is presented. Simulation of industrial circuits using this partitioning is up to 41% faster than with other known partitioning approaches for parallel analog simulation.
References
[1]
Paul Cox, Richard Burch, and Berton Epler. Circuit partitioning for parallel processing. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 186-189, 1986.
[2]
P. Debefve, F. Odeh, and A.E. Ruehli. Waveform techniques. In A.E. Ruehli, editor, Circuit Analysis, Simulation and Design, Part 2, volume 3 of Advances in CAD .for VLSI, chapter 8, pages 41-127'. North-Holland, 1985.
[3]
C.M. Fiduccia and R.M. Mattheyses. A linear-time heuristic for improving network partitions. In A GM/IEEE Design Automation Conference (DAC), volume 19, pages 175-181, 1982.
[4]
L. Hagen and A. B. Kahng. Fast spectral methods for ratio cut partitioning and clustering. In IEEE/A CM International Conference on Computer-Aided Design (ICCAD), pages 10-13, 1991.
[5]
W. John, W. Rissiek, and K.L. Paap. Circuit partitioning for waveform relaxation. In European Conference on Design Automation (EDA C), pages 149--153, Feb 1991. Amsterdam.
[6]
T. Kage, F. Kawafuji, and J. Niitsuma. A circuit partitioning approach for parallel circuit simulation. IEICE Transactions on Fundamentals, E77-A(3):461--466, 1994.
[7]
L. Nagel. SPICE2: A computer program to simulate semiconductor circuits. Ph.D. dissertation, Univ. of California, Berkeley, 1975.
[8]
Bernhard M. Riess, Konrad Doll, and Frank M. Johannes. Partitioning very large circuits using analytical placement techniques. In A CM/IEEE Design Automation Conference (DA C), pages 646-651, June 1994.
[9]
Bernhard M. Riess and Andreas A. Schoene. Architecture driven k-way partitioning for multichip modules. In European Design and Test Conference (ED~TC), pages 71-75, Paris, France, March 1995.
[10]
Alberto Sangiovanni-Vincentelli, Li-Kuan Ohen, and Leon O. Chua. An efficient heuristic cluster algorithm for tearing large-scale networks. IEEE Transactions on Gireuits and Systems CAS, CAS-24(12):709--717, Dec. 1977.
[11]
U. Wever and Q. Zheng. Parallel transient analysis for circuit simulation. In Proceedings o} the 29 Annual Hawaff International Conference on System Sciences, volume 1, pages 442--447, 1996.
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Published In
July 1997
184 pages
Copyright © 1997 Authors.
Publisher
Association for Computing Machinery
New York, NY, United States
Publication History
Published: 01 June 1997
Published in SIGSIM Volume 27, Issue 1
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