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Closed form solution to simultaneous buffer insertion/sizing and wire sizing

Authors:

Chris C. N. Chu,

D. F. WongAuthors Info & Claims

ISPD '97: Proceedings of the 1997 international symposium on Physical design

Pages 192 - 197

https://doi.org/10.1145/267665.267712

Published: 01 April 1997 Publication History

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Cited By

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Han MWang LXiao LCai TWang ZXu XZhang C(2024)ReDas: A Lightweight Architecture for Supporting Fine-Grained Reshaping and Multiple Dataflows on Systolic ArrayIEEE Transactions on Computers10.1109/TC.2024.339850073:8(1997-2011)Online publication date: Aug-2024
https://doi.org/10.1109/TC.2024.3398500
Bartoschek CHeld SRautenbach DVygen JNam GSaxena P(2009)Fast buffering for optimizing worst slack and resource consumption in repeater treesProceedings of the 2009 international symposium on Physical design10.1145/1514932.1514942(43-50)Online publication date: 29-Mar-2009
https://dl.acm.org/doi/10.1145/1514932.1514942
Xie YEachempati SYanamandra ANarayanan VIrwin M(2009)Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution networkProceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures10.1109/NANOARCH.2009.5226352(51-56)Online publication date: 30-Jul-2009
https://dl.acm.org/doi/10.1109/NANOARCH.2009.5226352
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Index Terms

Closed form solution to simultaneous buffer insertion/sizing and wire sizing
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Interconnection architectures
2. Hardware
  1. Integrated circuits
    1. Interconnect
  2. Very large scale integration design

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Information

Published In

ISPD '97: Proceedings of the 1997 international symposium on Physical design

April 1997

230 pages

ISBN:0897919270

DOI:10.1145/267665

Chairmen:
Andrew B. Kahng
Univ. of California, Los Angeles, and Cadence Design Systems, San Jose, CA
,
Majid Sarrafzadeh
Northwestern Univ., Evanston, IL

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 April 1997

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SIGDA

ISPD97: 1997 International Symposium on Physical Design

April 14 - 16, 1997

California, Napa Valley, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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Cited By

View all

Han MWang LXiao LCai TWang ZXu XZhang C(2024)ReDas: A Lightweight Architecture for Supporting Fine-Grained Reshaping and Multiple Dataflows on Systolic ArrayIEEE Transactions on Computers10.1109/TC.2024.339850073:8(1997-2011)Online publication date: Aug-2024
https://doi.org/10.1109/TC.2024.3398500
Bartoschek CHeld SRautenbach DVygen JNam GSaxena P(2009)Fast buffering for optimizing worst slack and resource consumption in repeater treesProceedings of the 2009 international symposium on Physical design10.1145/1514932.1514942(43-50)Online publication date: 29-Mar-2009
https://dl.acm.org/doi/10.1145/1514932.1514942
Xie YEachempati SYanamandra ANarayanan VIrwin M(2009)Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution networkProceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures10.1109/NANOARCH.2009.5226352(51-56)Online publication date: 30-Jul-2009
https://dl.acm.org/doi/10.1109/NANOARCH.2009.5226352
Hasani FMasoumi N(2008)Interconnect sizing and spacing with consideration of buffer insertion for simultaneous crosstalk-delay optimization2008 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era10.1109/DTIS.2008.4540218(1-6)Online publication date: Mar-2008
https://doi.org/10.1109/DTIS.2008.4540218
Peng YLiu XSentovich E(2006)Low-power repeater insertion with both delay and slew rate constraintsProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1146989(302-307)Online publication date: 24-Jul-2006
https://dl.acm.org/doi/10.1145/1146909.1146989
Bartoschek CHeld SRautenbach DVygen JScheffer L(2006)Efficient generation of short and fast repeater tree topologiesProceedings of the 2006 international symposium on Physical design10.1145/1123008.1123032(120-127)Online publication date: 9-Apr-2006
https://dl.acm.org/doi/10.1145/1123008.1123032
Vogel SWong MHirose F(2006)Closed form solution for optimal buffer sizing using the Weierstrass elliptic functionProceedings of the 2006 Asia and South Pacific Design Automation Conference10.1145/1118299.1118378(315-319)Online publication date: 24-Jan-2006
https://dl.acm.org/doi/10.1145/1118299.1118378
Peng YLiu X(2006)An Efficient Low-Power Repeater-Insertion SchemeIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2006.88260125:12(2726-2736)Online publication date: 1-Dec-2006
https://dl.acm.org/doi/10.1109/TCAD.2006.882601
Liu XPeng YPapaefthymiou M(2006)Practical repeater insertion for low powerIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2006.85596825:5(917-924)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TCAD.2006.855968
Alpert CHu JSapatnekar SSze C(2006)Accurate estimation of global buffer delay within a floorplanIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2005.85588925:6(1140-1145)Online publication date: 1-Jun-2006
https://dl.acm.org/doi/10.1109/TCAD.2005.855889
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