More Web Proxy on the site http://driver.im/

tutorial

Energy-Efficient Hadamard-Based SATD Architectures

Authors:

Luiz Henrique Cancellier,

André Beims Bräscher,

José Luís GüntzelAuthors Info & Claims

SBCCI '14: Proceedings of the 27th Symposium on Integrated Circuits and Systems Design

Article No.: 36, Pages 1 - 6

https://doi.org/10.1145/2660540.2661004

Published: 01 September 2014 Publication History

Abstract

In this paper we present energy-efficient Hadamard-based Sum of Absolute Transformed Differences (SATD) architectures. We relied on two state of the art methods for SATD, one using the Fast Hadamard Transform (FHT) butterfly and another one using the so-called Transform-Exempted (TE) SATD algorithm. Those were combined with architectural decisions, as the use of a transpose buffer. A total of six Hadamard-based SATD architectures were synthesized for a commercial 45 nm standard cell library. The best energy results are related to TE-SATD architectures: down to 7.62 pJ/SATD in the case of parallel architecture with pipeline. However, considering also the area results when evaluating energy, the best results are achieved when both methods are applied to the transpose buffer base architecture: nearly 10 pJ/SATD with up to 71% smaller area compared with parallel base architectures.

References

[1]

F. Bossen, B. Bross, K. Suhring, and D. Flynn. Hevc complexity and implementation analysis. IEEE Trans. Circuits Syst. Video Technol., 22(12):1685--1696, 2012.

Digital Library

[2]

J. S. Dominges Jr, V. N. Possani, D. S. Silveira, L. S. da Rosa Jr, and L. V. Agostini. High throughput 4x4 and 8x8 satd similarity criteria architectures for video coding applications. In 2011 VII Designer Forum (DF), page 115. Citeseer, 2011.

[3]

C.-P. Fan and J.-F. Yang. Fixed-pipeline two-dimensional hadamard transform algorithms. IEEE Trans. Signal Process., 45(6):1669--1674, Jun 1997.

Digital Library

[4]

C.-P. Fan and J.-F. Yang. Fast center weighted hadamard transform algorithms. IEEE Trans. Circuits Syst. II, 45(3):429--432, Mar 1998.

[5]

Y.-W. Huang, B.-Y. Hsieh, T.-C. Chen, and L.-G. Chen. Analysis, fast algorithm, and vlsi architecture design for h.264/avc intra frame coder. IEEE Trans. Circuits Syst. Video Technol., 15(3):378--401, March 2005.

Digital Library

[6]

ITU-T. H.264 corrigendum 1, jan 2009.

[7]

ITU-T. Recommendation itu-t h.265: High efficiency video coding. Recommendation H.265, International Telecommunication Union, Geneva, 2013.

[8]

JCT-VC. Hevc test model, 2013.

[9]

F. Jou. Method for fast satd estimation, Sept. 28 2010. US Patent 7,804,900.

[10]

J. Kim and J. Jeong. Fast intra mode decision algorithm using the sum of absolute transformed differences. In Digital Image Computing Techniques and Applications (DICTA), 2011 International Conference on, pages 655--659, Dec 2011.

Digital Library

[11]

V. d. S. Livramento, B. G. Moraes, B. A. Machado, E. Boabaid, and J. L. Güntzel. Evaluating the impact of architectural decisions on the energy efficiency of fdct/idct configurable ip cores. Journal of Integrated Circuits and Systems, 7(1):23--36, 2012.

[12]

L.-M. Po and K. Guo. Transform-domain fast sum of the squared difference computation for h.264/avc rate-distortion optimization. IEEE Trans. Circuits Syst. Video Technol., 17(6):765--773, 2007.

Digital Library

[13]

M. Porto, T. da Silva, R. Porto, L. Agostini, I. da Silva, and S. Bampi. Design space exploration on the H.264 4x4 hadamard transform. In NORCHIP Conference, 2005. 23rd, pages 188--191, Nov 2005.

[14]

W. Pratt, J. Kane, and H. C. Andrews. Hadamard transform image coding. Proceedings of the IEEE, 57(1):58--68, Jan 1969.

[15]

I. E. Richardson. The H.264 Advanced Video Compression Standard, Second Edition. John Wiley & Sons Ltd, 2010.

Digital Library

[16]

R. Rithe, C.-C. Cheng, and A. Chandrakasan. Quad full-hd transform engine for dual-standard low-power video coding. In Solid State Circuits Conference (A-SSCC), 2011 IEEE Asian, pages 401--404, Nov 2011.

[17]

N. Shenoy. Retiming: Theory and practice. Integr. VLSI J., 22(1--2):1--21, Aug. 1997.

Digital Library

[18]

G. Sullivan, J. Ohm, W.-J. Han, and T. Wiegand. Overview of the high efficiency video coding (HEVC) standard. IEEE Trans. Circuits Syst. Video Technol., 22(12):1649--1668, dez 2012.

Digital Library

[19]

Synopsys. Synopsys design compiler, version f-2011.09-sp5-2., 2011.

[20]

Synopsys. Synopsys's Design Compiler User Guide, Version I-2013.12-SP4., 2014.

[21]

TSMC. TSMC STANDARD CELL Library TCBN45GSBWPTC, 2011.

[22]

F. Walter, C. Diniz, and S. Bampi. Synthesis and comparison of low-power high-throughput architectures for sad calculation. Analog Integrated Circuits and Signal Processing, 73(3):873--884, 2012.

[23]

H. M. Wang, C.-H. Tseng, and J. F. Yang. Computation reduction for intra 4x4 mode decision with satd criterion in h.264/avc. Signal Processing, IET, 1(3):121--127, September 2007.

[24]

T.-C. Wang, Y.-W. Huang, H.-C. Fang, and L.-G. Chen. Parallel 4 times;4 2d transform and inverse transform architecture for mpeg-4 avc/h.264. In Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, volume 2, pages II--800--II--803 vol.2, May 2003.

[25]

T. Wiegand, G. Sullivan, G. Bjontegaard, and A. Luthra. Overview of the h.264/avc video coding standard. IEEE Trans. Circuits Syst. Video Technol., 13(7):560--576, July 2003.

Digital Library

[26]

H. Zhang and Z. Ma. Fast intra prediction for high efficiency video coding. In W. Lin, D. Xu, A. Ho, J. Wu, Y. He, J. Cai, M. Kankanhalli, and M.-T. Sun, editors, Advances in Multimedia Information Processing -- PCM 2012, volume 7674 of Lecture Notes in Computer Science, pages 568--577. Springer Berlin Heidelberg, 2012.

Digital Library

[27]

C. Zhu and B. Xiong. Transform-exempted calculation of sum of absolute hadamard transformed differences. IEEE Trans. Circuits Syst. Video Technol., 19(8):1183--1188, 2009.

Digital Library

Cited By

Partanen TLemmetti ASjovall PVanne J(2021)High-Level Synthesis Implementation of Transform-Exempted SATD Architectures for Low-Power Video Coding2021 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS51556.2021.9401399(1-5)Online publication date: May-2021
https://doi.org/10.1109/ISCAS51556.2021.9401399
Silveira BPaim GAbreu Bdos Santos Ferreira RDiniz Cda Costa EBampi S(2021)The 4-2 Fused Adder–Subtractor Compressor for Low-Power Butterfly-Based Hardware ArchitecturesCircuits, Systems, and Signal Processing10.1007/s00034-021-01839-xOnline publication date: 16-Sep-2021
https://doi.org/10.1007/s00034-021-01839-x
Seidel IMonteiro MBonotto BAgostini LGuntzel J(2019)Energy-Efficient Hadamard-Based SATD Hardware Architectures Through Calculation ReuseIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2019.290000466:6(2102-2115)Online publication date: Jun-2019
https://doi.org/10.1109/TCSI.2019.2900004
Show More Cited By

Index Terms

Energy-Efficient Hadamard-Based SATD Architectures
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design

Recommendations

Transform-exempted calculation of sum of absolute Hadamard transformed differences

Sum of absolute Hadamard transformed differences (SATD) is an important distortion metric applied in the latest video coding standard H.264/AVC, which is an alternative to the sum of absolute differences (SAD) to improve coding efficiency. However, the ...
Faster Walsh-Hadamard and Discrete Fourier Transforms from Matrix Non-rigidity
STOC 2023: Proceedings of the 55th Annual ACM Symposium on Theory of Computing

We give algorithms with lower arithmetic operation counts for both the Walsh-Hadamard Transform (WHT) and the Discrete Fourier Transform (DFT) on inputs of power-of-2 size N.
For the WHT, our new algorithm has an operation count of 23/24N logN + O(N). ...
Sequency-ordered generalized Walsh-Fourier transform

A new transform family, called the sequency-ordered generalized Walsh-Fourier transform (SGWFT), is proposed in this paper. Using the kernel matrix generation process and the controllable phase quantization parameter, the Walsh-Hadamard transform (WHT), ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences

SBCCI '14: Proceedings of the 27th Symposium on Integrated Circuits and Systems Design

September 2014

286 pages

ISBN:9781450331562

DOI:10.1145/2660540

Conference Chairs:
Edward David,
Moreno Ordonez,
Program Chairs:
Rodolfo Jardim de Azevedo,
Peter Kinget

Copyright © 2014 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

IEEE ICAS
SBC: Brazilian Computer Society
IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
SBMICRO: Brazilian Microelectronics Society

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 September 2014

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Tutorial
Research
Refereed limited

Conference

SBCCI '14

Sponsor:

SBC
SIGDA
SBMICRO

SBCCI '14: 27th Symposium on Integrated Circuits and Systems Design

September 1 - 5, 2014

Aracaju, Brazil

Acceptance Rates

SBCCI '14 Paper Acceptance Rate 40 of 130 submissions, 31%;

Overall Acceptance Rate 133 of 347 submissions, 38%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

9
Total Citations
View Citations
70
Total Downloads

Downloads (Last 12 months)3
Downloads (Last 6 weeks)1

Reflects downloads up to 15 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

Partanen TLemmetti ASjovall PVanne J(2021)High-Level Synthesis Implementation of Transform-Exempted SATD Architectures for Low-Power Video Coding2021 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS51556.2021.9401399(1-5)Online publication date: May-2021
https://doi.org/10.1109/ISCAS51556.2021.9401399
Silveira BPaim GAbreu Bdos Santos Ferreira RDiniz Cda Costa EBampi S(2021)The 4-2 Fused Adder–Subtractor Compressor for Low-Power Butterfly-Based Hardware ArchitecturesCircuits, Systems, and Signal Processing10.1007/s00034-021-01839-xOnline publication date: 16-Sep-2021
https://doi.org/10.1007/s00034-021-01839-x
Seidel IMonteiro MBonotto BAgostini LGuntzel J(2019)Energy-Efficient Hadamard-Based SATD Hardware Architectures Through Calculation ReuseIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2019.290000466:6(2102-2115)Online publication date: Jun-2019
https://doi.org/10.1109/TCSI.2019.2900004
Monteiro MSeidel IGuntzel J(2018)On the calculation reuse in hadamard-based SATD2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS)10.1109/LASCAS.2018.8399925(1-4)Online publication date: Feb-2018
https://doi.org/10.1109/LASCAS.2018.8399925
Silveira BFerreira RPaim GDiniz CCosta E(2017)Low power SATD architecture employing multiple sizes Hadamard Transforms and adder compressors2017 15th IEEE International New Circuits and Systems Conference (NEWCAS)10.1109/NEWCAS.2017.8010159(277-280)Online publication date: Jun-2017
https://doi.org/10.1109/NEWCAS.2017.8010159
Silveira BAbreu BPaim GGreller MFerreira RDiniz CCosta EBampi S(2017)Using adder and subtractor compressors to sum of absolute transformed differences architecture for low-power video encoding2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS)10.1109/ICECS.2017.8292076(409-493)Online publication date: Dec-2017
https://doi.org/10.1109/ICECS.2017.8292076
Zhu SZhang C(2017)A fast algorithm of intra prediction modes pruning for HEVC based on decision trees and a new three-step searchMultimedia Tools and Applications10.1007/s11042-016-4056-076:20(21707-21728)Online publication date: 1-Oct-2017
https://dl.acm.org/doi/10.1007/s11042-016-4056-0
Seidel IBeims Brascher AGuntzel JAgostini L(2016)Energy-efficient SATD for beyond HEVC2016 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2016.7527362(802-805)Online publication date: May-2016
https://doi.org/10.1109/ISCAS.2016.7527362
Silveira EDiniz CBeck Fonseca MCosta E(2015)SATD hardware architecture based on 8×8 Hadamard Transform for HEVC encoder2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)10.1109/ICECS.2015.7440382(576-579)Online publication date: Dec-2015
https://doi.org/10.1109/ICECS.2015.7440382

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents