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Layout driven re-synthesis for low power consumption LSIs

Authors:

Masako Murofushi,

Takashi Ishioka,

Masami Murakata,

Takashi MitsuhashiAuthors Info & Claims

DAC '97: Proceedings of the 34th annual Design Automation Conference

Pages 666 - 669

https://doi.org/10.1145/266021.266314

Published: 13 June 1997 Publication History

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Abstract

A new technology re-mapping method named LDR (LayoutDriven Re-synthesis), which is applied after placement, is proposed.LDR executes re-mapping and re-placement simultaneouslyin order to minimize power consumption with placementinformation.High switching activity nets are concealed insidethe re-mapped cells or are shortened by re-placement in LDR.To estimate power consumption, LDR uses static power estimatorfor combinational circuits.LDR also calculates wirecapacitances accurately based on placement information toevaluate power.Experimental results show that 20% powerreduction compared with original circuits is performed by proposed method.

References

[1]

Kamal Chaudhary and Massoud Pedram : "A near optimal algorithm for technology mapping minimizing area under delay constraints", Proc. Desi9n Automation Conf., pp. 492- 498 (1992).

Digital Library

Google Scholar

[2]

Chi-Ying Tsui, Massoud Pedram and Alvin M. DespMn : "Technology decomposition and mapping targeting low power dessipation', Proc. Desi9n Automation Conf., pp. 68-73 (1993).

Digital Library

Google Scholar

[3]

De-Sheng Chen and Majid Sarrafzadeh : "An Exact Algorithm for Low Power Library-Specific Gate Re-Sizing", Proc. Desi9n Automation Conf., pp. 782-788 (1996).

Digital Library

Google Scholar

[4]

H. Vaishnav and Massoud Pedram : "Pcube:A Performance Driven Placement Algorithm for Low Power Designs", Proc. European Desi9n Automation Conf., pp. 72-77 (1993).

Google Scholar

[5]

Massoud Pedram and Narasimha Bhat : "Layout driven technology mapping", Proc. Desi9n Automation Conf., pp. 99-105 (1991).

Digital Library

Google Scholar

[6]

Lalgudi N. Kannan, Peter R. Suaris and Hong-Gee Fang : "A methodology and algorithms for post-placement delay optimization", Proc. Desi9n Automation Conf., pp. 327-332 (1994).

Digital Library

Google Scholar

[7]

Taku Uchino, Fumihiro Minami, Takashi Mitsuhashi and Nobuyuki Goto : "Switching activity using boolean approximation method", Proc. Desi9n Automation Conf., pp. 20- 25 (1995).

Digital Library

Google Scholar

[8]

Mutsunori Igarashi, Masako Murofushi and Masami Murakata, "Timing Divert Placement with an RC wire Delay Model for Sub-Micron CMOS Gate-Arrays", SASIMI '93. (1993).

Google Scholar

Cited By

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Liu QMarek-Sadowska MGroeneveld PScheffer L(2005)Wire length prediction-based technology mapping and fanout optimizationProceedings of the 2005 international symposium on Physical design10.1145/1055137.1055167(145-151)Online publication date: 3-Apr-2005
https://dl.acm.org/doi/10.1145/1055137.1055167
Liu QMarek-Sadowska MMalik SFix LKahng A(2004)Pre-layout wire length and congestion estimationProceedings of the 41st annual Design Automation Conference10.1145/996566.996726(582-587)Online publication date: 7-Jun-2004
https://dl.acm.org/doi/10.1145/996566.996726
Farrahi AHathaway DWang MSarrafzadeh M(2000)Quality of EDA CAD ToolsProceedings of the 1st International Symposium on Quality of Electronic Design10.5555/850998.855839Online publication date: 20-Mar-2000
https://dl.acm.org/doi/10.5555/850998.855839
Show More Cited By

Index Terms

Layout driven re-synthesis for low power consumption LSIs

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Information

Published In

DAC '97: Proceedings of the 34th annual Design Automation Conference

June 1997

788 pages

ISBN:0897919203

DOI:10.1145/266021

Chairmen:
Ellen J. Yoffa
IBM T. J. Watson Research Center, Yorktown Heights, NY
,
Giovanni De Micheli
Stanford Univ., Stanford, CA
,
Jan M. Rabaey
Univ. of California, Berkeley

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 1997

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DAC97

Sponsor:

EDAC
SIGDA
IEEE-CAS

DAC97: The 34th Design Automation Conference

June 9 - 13, 1997

California, Anaheim, USA

Acceptance Rates

DAC '97 Paper Acceptance Rate 139 of 400 submissions, 35%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

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Cited By

View all

Liu QMarek-Sadowska MGroeneveld PScheffer L(2005)Wire length prediction-based technology mapping and fanout optimizationProceedings of the 2005 international symposium on Physical design10.1145/1055137.1055167(145-151)Online publication date: 3-Apr-2005
https://dl.acm.org/doi/10.1145/1055137.1055167
Liu QMarek-Sadowska MMalik SFix LKahng A(2004)Pre-layout wire length and congestion estimationProceedings of the 41st annual Design Automation Conference10.1145/996566.996726(582-587)Online publication date: 7-Jun-2004
https://dl.acm.org/doi/10.1145/996566.996726
Farrahi AHathaway DWang MSarrafzadeh M(2000)Quality of EDA CAD ToolsProceedings of the 1st International Symposium on Quality of Electronic Design10.5555/850998.855839Online publication date: 20-Mar-2000
https://dl.acm.org/doi/10.5555/850998.855839
Donath WKudva PStok LReddy LSullivan AChakraborty KVillarrubia PBolsens I(2000)Transformational placement and synthesisProceedings of the conference on Design, automation and test in Europe10.1145/343647.343732(194-201)Online publication date: 1-Jan-2000
https://dl.acm.org/doi/10.1145/343647.343732
Farrahi AHathaway DWang MSarrafzadeh M(2000)Quality of EDA CAD tools: definitions, metrics and directionsProceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)10.1109/ISQED.2000.838903(395-405)Online publication date: 2000
https://doi.org/10.1109/ISQED.2000.838903
Yu-Liang Wu Wangning Long Hongbing Fan (2000)A fast graph-based alternative wiring scheme for Boolean networksVLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design10.1109/ICVD.2000.812620(268-273)Online publication date: 2000
https://doi.org/10.1109/ICVD.2000.812620
Donath WKudva PStok LVillarrubia PReddy LSullivan A(2000)Transformational placement and synthesisProceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537)10.1109/DATE.2000.840038(194-201)Online publication date: 2000
https://doi.org/10.1109/DATE.2000.840038

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Algorithms for VLSI layout synthesis

Low-Power Driven Logic Synthesis Using Accurate Power Estimation Technique

Low Power Gated Clock Tree Driven Placement