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More practical bounded-skew clock routing

Authors:

Andrew B. Kahng,

C.-W. Albert TsaoAuthors Info & Claims

DAC '97: Proceedings of the 34th annual Design Automation Conference

Pages 594 - 599

https://doi.org/10.1145/266021.266292

Published: 13 June 1997 Publication History

Abstract

Academic clock routing research results has often hadlimited impact on industry practice, since such practical considerationsas hierarchical buffering, rise-time and overshoot constraints,obstacle- and legal location-checking, varying layer parasitics andcongestion, and even the underlying design flow are often ignored.This paper explores directions in which traditional formulationscan be extended so that the resulting algorithms are more usefulin production design environments. Specifically, the following issuesare addressed: (i) clock routing for varying layer parasiticswith nonzero via parasitics; (ii) obstacle-avoidance clock routing;(iii) a new topology design rule for prescribed-delay clock routing;and (iv) predictive modeling of the clock routing itself. Wedevelop new theoretical analyses and heuristics, and present experimentalresults that validate our new approaches.

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Cited By

Bairamkulov RFriedman EBairamkulov RFriedman E(2022)Synchronization in VLSIGraphs in VLSI10.1007/978-3-031-11047-4_4(101-147)Online publication date: 30-Jun-2022
https://doi.org/10.1007/978-3-031-11047-4_4
Kim TKim TLin Y(2010)Clock tree embedding for 3D ICsProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899837(486-491)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899837
Shih XCheng CHo YChang YLin Y(2010)Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimizationProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899818(395-400)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899818
Show More Cited By

Index Terms

More practical bounded-skew clock routing

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Information

Published In

cover image ACM Conferences

DAC '97: Proceedings of the 34th annual Design Automation Conference

June 1997

788 pages

ISBN:0897919203

DOI:10.1145/266021

Chairmen:
Ellen J. Yoffa
IBM T. J. Watson Research Center, Yorktown Heights, NY
,
Giovanni De Micheli
Stanford Univ., Stanford, CA
,
Jan M. Rabaey
Univ. of California, Berkeley

Copyright © 1997 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS: Circuits & Systems

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 1997

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DAC97

Sponsor:

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IEEE-CAS

DAC97: The 34th Design Automation Conference

June 9 - 13, 1997

California, Anaheim, USA

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DAC '97 Paper Acceptance Rate 139 of 400 submissions, 35%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

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62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

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Cited By

Bairamkulov RFriedman EBairamkulov RFriedman E(2022)Synchronization in VLSIGraphs in VLSI10.1007/978-3-031-11047-4_4(101-147)Online publication date: 30-Jun-2022
https://doi.org/10.1007/978-3-031-11047-4_4
Kim TKim TLin Y(2010)Clock tree embedding for 3D ICsProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899837(486-491)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899837
Shih XCheng CHo YChang YLin Y(2010)Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimizationProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899818(395-400)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899818
Kim TKim T(2010)Clock tree embedding for 3D ICs2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2010.5419833(486-491)Online publication date: Jan-2010
https://doi.org/10.1109/ASPDAC.2010.5419833
Wang DSuaris PChou N(2003)A Practical ASIC Methodology for Flexible Clock Tree Synthesis with Routing BlockagesIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation10.1007/978-3-540-39762-5_57(511-519)Online publication date: 2003
https://doi.org/10.1007/978-3-540-39762-5_57
Liu IChou TAziz AWong DWiesel MHill D(2000)Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertionProceedings of the 2000 international symposium on Physical design10.1145/332357.332370(33-38)Online publication date: 1-May-2000
https://dl.acm.org/doi/10.1145/332357.332370
Chen YKahng AQu GZelikovsky AWhite JSentovich E(1999)The associative-skew clock routing problemProceedings of the 1999 IEEE/ACM international conference on Computer-aided design10.5555/339492.339616(168-172)Online publication date: 7-Nov-1999
https://dl.acm.org/doi/10.5555/339492.339616

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