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Multi-way FPGA partitioning by fully exploiting design hierarchy

Authors:

Wen-Jong Fang,

Allen C.-H. WuAuthors Info & Claims

DAC '97: Proceedings of the 34th annual Design Automation Conference

Pages 518 - 521

https://doi.org/10.1145/266021.266270

Published: 13 June 1997 Publication History

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Abstract

In this paper, we present a new integrated synthesisand partitioning method for multiple-FPGA applications.This method first synthesizes a design specificationin a fine-grained way so that functional clusters can bepreserved based on the structural nature of the designspecification.Then, it applies a hierarchical set-coveringpartitioning method to form the final FPGA partitionings.Our approach bridges the gap between HDL synthesisand physical partitioning by fully exploiting the designhierarchy.Experimental results on a number of benchmarksand industrial designs demonstrate that I/O limitsare the bottleneck for CLB utilization when applying atraditional multiple-FPGA synthesis method on flattenednetlists.In contrast, by fully exploiting the design structuralhierarchy during the multiple-FPGA partitioning,our proposed method produces fewer FPGA partitionswith higher CLB and low I/O-pin utilizations.

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Cited By

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Pistorius JLegai EMinoux MWong D(1999)Generation of very large circuits to benchmark the partitioning of FPGAProceedings of the 1999 international symposium on Physical design10.1145/299996.300026(67-73)Online publication date: 12-Apr-1999
https://dl.acm.org/doi/10.1145/299996.300026
Fang WWu AChawla BBryant RRabaey J(1998)Performance-driven multi-FPGA partitioning using functional clustering and replicationProceedings of the 35th annual Design Automation Conference10.1145/277044.277125(283-286)Online publication date: 1-May-1998
https://dl.acm.org/doi/10.1145/277044.277125
David JLegat J(1998)A data-flow oriented co-design for reconfigurable systemsProceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)10.1109/IWRSP.1998.676693(207-211)Online publication date: 1998
https://doi.org/10.1109/IWRSP.1998.676693
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Multi-way FPGA partitioning by fully exploiting design hierarchy

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Published In

DAC '97: Proceedings of the 34th annual Design Automation Conference

June 1997

788 pages

ISBN:0897919203

DOI:10.1145/266021

Chairmen:
Ellen J. Yoffa
IBM T. J. Watson Research Center, Yorktown Heights, NY
,
Giovanni De Micheli
Stanford Univ., Stanford, CA
,
Jan M. Rabaey
Univ. of California, Berkeley

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 1997

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DAC97: The 34th Design Automation Conference

June 9 - 13, 1997

California, Anaheim, USA

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DAC '97 Paper Acceptance Rate 139 of 400 submissions, 35%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Pistorius JLegai EMinoux MWong D(1999)Generation of very large circuits to benchmark the partitioning of FPGAProceedings of the 1999 international symposium on Physical design10.1145/299996.300026(67-73)Online publication date: 12-Apr-1999
https://dl.acm.org/doi/10.1145/299996.300026
Fang WWu AChawla BBryant RRabaey J(1998)Performance-driven multi-FPGA partitioning using functional clustering and replicationProceedings of the 35th annual Design Automation Conference10.1145/277044.277125(283-286)Online publication date: 1-May-1998
https://dl.acm.org/doi/10.1145/277044.277125
David JLegat J(1998)A data-flow oriented co-design for reconfigurable systemsProceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237)10.1109/IWRSP.1998.676693(207-211)Online publication date: 1998
https://doi.org/10.1109/IWRSP.1998.676693
Fang WWu A(1998)Integrating HDL Synthesis and Partitioning for Multi-FPGA DesignsIEEE Design & Test10.1109/54.67920915:2(65-72)Online publication date: 1-Apr-1998
https://dl.acm.org/doi/10.1109/54.679209

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Multiway FPGA partitioning by fully exploiting design hierarchy

Spectral-based multi-way FPGA partitioning

SPECTRAL-BASED MULTI-WAY FPGA PARTITIONING