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Functional ECO Using Metal-Configurable Gate-Array Spare Cells

Authors:

Iris Hui-Ru Jiang,

Yao-Wen ChangAuthors Info & Claims

DAC '14: Proceedings of the 51st Annual Design Automation Conference

Pages 1 - 6

https://doi.org/10.1145/2593069.2593145

Published: 01 June 2014 Publication History

Abstract

Metal-configurable gate-array spare cells, which have versatile functionality, are developed to overcome the inflexibility of standard spare cells used in conventional metal-only engineering change order (ECO). In this paper, we focus on functional ECO optimization using the new type of spare cells to fully exploit its strength. We observe that this functional ECO problem has the nature of dynamic logical and physical costs for selecting spare gate arrays. Unlike existing functional ECO works, which perform technology mapping based on ECO patches, we perform reverse mapping from spare gate arrays to handle these dynamic costs. We devise a spare array relation graph to record geometrical adjacency among spare gate arrays and interleave with the and-inverter network of ECO patches. To avoid redundant traversal and monitor the dynamic costs, we adopt A* search to simultaneously traverse and map between the logical ECO network and the physical spare array relation graph.

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Cited By

Pradhan MBhattacharya BChakrabarty KBhattacharya B(2019)Predicting ${X}$ -Sensitivity of Circuit-Inputs on Test-Coverage: A Machine-Learning ApproachIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.287816938:12(2343-2356)Online publication date: Dec-2019
https://doi.org/10.1109/TCAD.2018.2878169

Index Terms

Functional ECO Using Metal-Configurable Gate-Array Spare Cells
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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Published In

cover image ACM Other conferences

DAC '14: Proceedings of the 51st Annual Design Automation Conference

June 2014

1249 pages

ISBN:9781450327305

DOI:10.1145/2593069

Copyright © 2014 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGBED: ACM Special Interest Group on Embedded Systems
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 2014

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DAC '14

DAC '14: The 51st Annual Design Automation Conference 2014

June 1 - 5, 2014

CA, San Francisco, USA

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Cited By

Pradhan MBhattacharya BChakrabarty KBhattacharya B(2019)Predicting ${X}$ -Sensitivity of Circuit-Inputs on Test-Coverage: A Machine-Learning ApproachIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.287816938:12(2343-2356)Online publication date: Dec-2019
https://doi.org/10.1109/TCAD.2018.2878169

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