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Architectural implications of hardware-accelerated bucket rendering on the PC

Authors:

Michael Cox,

Narendra BhandariAuthors Info & Claims

HWWS '97: Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware

Pages 25 - 34

https://doi.org/10.1145/258694.258706

Published: 03 August 1997 Publication History

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Wang PYang CChen YCheng Y(2011)Power gating strategies on GPUsACM Transactions on Architecture and Code Optimization10.1145/2019608.20196128:3(1-25)Online publication date: 18-Oct-2011
https://dl.acm.org/doi/10.1145/2019608.2019612
Yeh CLin CChiou WHuang I(2010)Exploration of tile/triangle-based rendering approaches for 3D graphics SoC2010 International Symposium on Next Generation Electronics10.1109/ISNE.2010.5669157(227-230)Online publication date: Nov-2010
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Shen SLee SChen C(2010)Full system simulation with QEMU: An approach to multi-view 3D GPU designProceedings of 2010 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2010.5537690(3877-3880)Online publication date: May-2010
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Architectural implications of hardware-accelerated bucket rendering on the PC

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Published In

HWWS '97: Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware

August 1997

160 pages

ISBN:0897919610

DOI:10.1145/258694

Chairmen:
Arie Kaufman
State Univ. of New York at Stony Brook, Stony Brook, NY
,
Wolfgang Straßer
Univ. of Tu¨bingen
,
Steven Molnar
HP Chapel Hill Graphics Lab
,
Bengt-Olaf Schneider
IBM T.J. Watson Research Center, Yorktown Heights, NY

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 August 1997

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ESWGH97

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SIGGRAPH
EUROGRAPHICS

ESWGH97: The 1997 Eurographics/Siggraph Workshop on Graphics Hardware

August 3 - 4, 1997

California, Los Angeles, USA

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Cited By

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Wang PYang CChen YCheng Y(2011)Power gating strategies on GPUsACM Transactions on Architecture and Code Optimization10.1145/2019608.20196128:3(1-25)Online publication date: 18-Oct-2011
https://dl.acm.org/doi/10.1145/2019608.2019612
Yeh CLin CChiou WHuang I(2010)Exploration of tile/triangle-based rendering approaches for 3D graphics SoC2010 International Symposium on Next Generation Electronics10.1109/ISNE.2010.5669157(227-230)Online publication date: Nov-2010
https://doi.org/10.1109/ISNE.2010.5669157
Shen SLee SChen C(2010)Full system simulation with QEMU: An approach to multi-view 3D GPU designProceedings of 2010 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2010.5537690(3877-3880)Online publication date: May-2010
https://doi.org/10.1109/ISCAS.2010.5537690
Zhu HWang LChan T(2009)Parallel and Distributed Visualization AdvancesEncyclopedia of Information Science and Technology, Second Edition10.4018/978-1-60566-026-4.ch482(3018-3025)Online publication date: 2009
https://doi.org/10.4018/978-1-60566-026-4.ch482
Hsieh HHsiao CYang HChung CShann J(2009)Methods for Precise False-Overlap Detection in Tile-Based RenderingProceedings of the 2009 International Conference on Computational Science and Engineering - Volume 0210.1109/CSE.2009.466(414-419)Online publication date: 29-Aug-2009
https://dl.acm.org/doi/10.1109/CSE.2009.466
Juurlink BAntochi ICrisu DCotofana SVassiliadis S(2008)GRAALIEEE Computer Graphics and Applications10.1109/MCG.2008.7228:4(63-73)Online publication date: 1-Jul-2008
https://dl.acm.org/doi/10.1109/MCG.2008.72
Abraham FCeles WCerqueira RCampos J(2004)A load-balancing strategy for sort-first distributed renderingProceedings. 17th Brazilian Symposium on Computer Graphics and Image Processing10.1109/SIBGRA.2004.1352973(292-299)Online publication date: 2004
https://doi.org/10.1109/SIBGRA.2004.1352973
Antochi IJuurlink BVassiliadis SLiuha P(2004)Efficient tile-aware bounding-box overlap test for tile-based rendering2004 International Symposium on System-on-Chip, 2004. Proceedings.10.1109/ISSOC.2004.1411177(165-172)Online publication date: 2004
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Antochi IJuurlink BVassiliadis SLiuha P(2004)Scene management models and overlap tests for tile-based renderingEuromicro Symposium on Digital System Design, 2004. DSD 2004.10.1109/DSD.2004.1333306(424-431)Online publication date: 2004
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Antochi IJuurlink BVassiliadis SLiuha P(2004)Memory Bandwidth Requirements of Tile-Based RenderingComputer Systems: Architectures, Modeling, and Simulation10.1007/978-3-540-27776-7_34(323-332)Online publication date: 2004
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