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Performance evaluation and prediction for parallel algorithms on the BBN GP1000

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Dennis GannonAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 18, Issue 3b

Pages 401 - 413

https://doi.org/10.1145/255129.255182

Published: 01 June 1990 Publication History

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Abstract

The techniques of “load/store” memory reference modeling is based on deriving performance characteristics of the memory architecture of a computer by looking at the behavior of simple sequences of load, store and nop (null operation) instructions. The resulting data base can be used to match load/store templates against algorithm kernels to predict performance or as a source of data for testing analytical models of the architecture. In this paper we study the BBN GP1000 parallel processing system. We show how to build a subset of the load/store kernels needed to characterize the machine and illustrate the behavior of a simple model based on the data.

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Cited By

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Arya Samman FHollstein TGlesner M(2018)Wormhole cut-through switchingMicroprocessors & Microsystems10.1016/j.micpro.2011.01.00335:3(343-358)Online publication date: 28-Dec-2018
https://dl.acm.org/doi/10.1016/j.micpro.2011.01.003
Lin YYou YHuang CLee JShih WHwang T(2007)Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domainsThe Journal of Supercomputing10.1007/s11227-007-0132-642:2(201-223)Online publication date: 1-Nov-2007
https://dl.acm.org/doi/10.1007/s11227-007-0132-6
Zhang X(2006)Dynamic and static load balancing for solving block bordered circuit equations on multiprocessorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.15999411:9(1086-1094)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.159994
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Performance evaluation and prediction for parallel algorithms on the BBN GP1000

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Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 18, Issue 3b

Special Issue: Proceedings of the 4th international conference on Supercomputing

Sept. 1990

489 pages

ISSN:0163-5964

DOI:10.1145/255129

Chairmen:
Ahmed Sameh
Univ. of Illinois at Urbana-Champaign, Urbana
,
Henk van der Vorst
Delft Univ. of Technology and CWI, The Netherlands

Issue’s Table of Contents

ICS '90: Proceedings of the 4th international conference on Supercomputing
June 1990
492 pages
ISBN:0897913698
DOI:10.1145/77726
Chairmen:
Ahmed Sameh
Univ. of Illinois
,
Henk van der Vorst
Delft Univ. of Technology and CWI, The Netherlands

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1990

Published in SIGARCH Volume 18, Issue 3b

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Cited By

View all

Arya Samman FHollstein TGlesner M(2018)Wormhole cut-through switchingMicroprocessors & Microsystems10.1016/j.micpro.2011.01.00335:3(343-358)Online publication date: 28-Dec-2018
https://dl.acm.org/doi/10.1016/j.micpro.2011.01.003
Lin YYou YHuang CLee JShih WHwang T(2007)Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domainsThe Journal of Supercomputing10.1007/s11227-007-0132-642:2(201-223)Online publication date: 1-Nov-2007
https://dl.acm.org/doi/10.1007/s11227-007-0132-6
Zhang X(2006)Dynamic and static load balancing for solving block bordered circuit equations on multiprocessorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.15999411:9(1086-1094)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.159994
Lin YHuang CLee JTang T(2005)System-level design space exploration for security processor prototyping in analytical approachesProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120873(376-380)Online publication date: 18-Jan-2005
https://dl.acm.org/doi/10.1145/1120725.1120873
Yung Chia Lin Chung Wen Huang Jenq Kuen Lee (2005)System-level design space exploration for security processor prototyping in analytical approachesProceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.10.1109/ASPDAC.2005.1466192(376-380)Online publication date: 2005
https://doi.org/10.1109/ASPDAC.2005.1466192
Sakellariou R(2005)Estimating the parallel start-up overhead for parallelizing compilersParallel Computing Technologies10.1007/3-540-63371-5_10(83-93)Online publication date: 9-Jun-2005
https://doi.org/10.1007/3-540-63371-5_10
Lin YYou YHuang CLee JShih WHwang T(2004)Power-Aware scheduling for parallel security processors with analytical modelsProceedings of the 17th international conference on Languages and Compilers for High Performance Computing10.1007/11532378_33(470-484)Online publication date: 22-Sep-2004
https://dl.acm.org/doi/10.1007/11532378_33
Triantafyllis SVachharajani MVachharajani NAugust DJohnson RConte THwu W(2003)Compiler optimization-space explorationProceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization10.5555/776261.776284(204-215)Online publication date: 23-Mar-2003
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Triantafyllis SVachharajani MVachharajani NAugust D(2003)Compiler optimization-space explorationInternational Symposium on Code Generation and Optimization, 2003. CGO 2003.10.1109/CGO.2003.1191546(204-215)Online publication date: 2003
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Durand DMontaut TKervella LJalby W(1996)Impact of Memory Contention on Dynamic Scheduling on NUMA MultiprocessorsIEEE Transactions on Parallel and Distributed Systems10.1109/71.5443597:11(1201-1214)Online publication date: 1-Nov-1996
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Abstract

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A bulk-synchronous parallel library implementation for the BBN butterfly GP1000